9SQL4954BNLGI Datasheet 9SQL4954BNLGI, 9SQL4954BNLGI8 | P10-P12

4-OUTPUT CK420BQ DERIVATIVE 10 NOVEMBER 4, 2016

9SQL4954 DATASHEET

Electrical Characteristics– REF

TA = T

AMB;

Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Lon

Accuracy ppm see Tperiod min-max values ppm 1,2

Clock period T

eriod

25 MHz output 40 ns 2

Output High Voltage V

= -2mA

0.8x

DDRE

Output Low Voltage V

= 2mA

0.2x

DDRE

Rise/Fall Slew Rate t

rf1

Byte 3 = 1F, V

= VDD-0.45V, V

= 0.45V 0.6 0.8 1.5 V/ns 1

Rise/Fall Slew Rate t

rf1

Byte 3 = 5F, V

= VDD-0.45V, V

= 0.45V 1.0 1.5 2.5 V/ns 1,3

Rise/Fall Slew Rate t

rf1

Byte 3 = 9F, V

= VDD-0.45V, V

= 0.45V 1.5 2.2 2.9 V/ns 1

Rise/Fall Slew Rate t

rf1

Byte 3 = DF, V

= VDD-0.45V, V

= 0.45V 1.9 2.9 3.9 V/ns 1

Duty Cycle d

t1X

= VDD/2 V 45 49.8 55 % 1,4

Duty Cycle Distortion d

tcd

= VDD/2 V -1 0 0 % 1,5

Jitter, cycle to cycle t

c-c

= VDD/2 V 81 250 ps 1,4

Noise floor t

dBc1k

1kHz offset -137 dBc 1,4

Noise floor t

dBc10k

10kHz offset to Nyquist -145 dBc 1,4

Jitter, phase t

hRE

12kHz to 5MHz, SSC Off 0.14 0.2 ps (rms) 1,4

Jitter, phase t

jphREF

12kHz to 5MHz, SSC On 0.64 1 ps (rms) 1,4

Guaranteed by design and characterization, not 100% tested in production.

Default SMBus Value

When driven by a crystal.

When driven by an external oscillator via the X1 pin, X2 should be floating.

All Lon

Term Accuracy and Clock Period specifications are

uaranteed assumin

that REF is trimmed to 25.00 MHz

NOVEMBER 4, 2016 11 4-OUTPUT CK420BQ DERIVATIVE

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General SMBus Serial Interface Information

How to Write

• Controller (host) sends a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) sends the byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through Byte

N+X-1

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

Note: SMBus Read/Write Address is Latched on SADR

pin.

How to Read

• Controller (host) will send a start bit

• Controller (host) sends the write address

• IDT clock will acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit

• Controller (host) sends the read address

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N+X-1

• IDT clock sends Byte 0 through Byte X (if X

(H)

was

written to Byte 8)

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

Index Block Write Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

Data Byte Count = X

ACK

Beginning Byte N

X Byte

ACK

O O

Byte N + X - 1

ACK

PstoP bit

Index Block Read Operation

Controller (Host) IDT (Slave/Receiver)

TstarT bit

Slave Address

WR WRite

ACK

Beginning Byte = N

ACK

RT Repeat starT

Slave Address

RD ReaD

ACK

Data Byte Count=X

ACK

X Byte

Beginning Byte N

ACK

O O

Byte N + X - 1

N Not acknowledge

PstoP bit

4-OUTPUT CK420BQ DERIVATIVE 12 NOVEMBER 4, 2016

9SQL4954 DATASHEET

SMBus Table: Output Enable Register

Byte 0 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

BCLK OE3 Output Enable RW Pin Control 1

Bit 2

BCLK OE2 Output Enable RW Pin Control 1

Bit 1

BCLK OE1 Output Enable RW Pin Control 1

Bit 0

BCLK OE0 Output Enable RW Pin Control 1

SMBus Table: SS Readback and Vhigh Control Register

Byte 1 Name Control Function Type 0 1 Default

Bit 7

SSENRB1 SS Enable Readback Bit1

Latch

Bit 6

SSENRB1 SS Enable Readback Bit0

Latch

Bit 5

SSEN_SWCNTRL Enable SW control of SS RW SS control locked

Values in B1[4:3]

control SS amount.

Bit 4

SSENSW1 SS Enable Software Ctl Bit1

Bit 3

SSENSW0* SS Enable Software Ctl Bit0

Bit 2

Bit 1

AMPLITUDE 1 RW 00 = 0.6V 01= 0.68V 1

Bit 0

AMPLITUDE 0 RW 10 = 0.75V 11 = 0.85V 0

SMBus Table: BCLK Slew Rate Control Register

Byte 2 Name Control Function Type 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

SLEWRATESEL BCLK3 Adjust Slew Rate of BCLK3 RW Slow Setting Fast Setting 1

Bit 2

SLEWRATESEL BCLK2 Adjust Slew Rate of BCLK2 RW Slow Setting Fast Setting 1

Bit 1

SLEWRATESEL BCLK1 Adjust Slew Rate of BCLK1 RW Slow Setting Fast Setting 1

Bit 0

SLEWRATESEL BCLK0 Adjust Slew Rate of BCLK0 RW Slow Setting Fast Setting 1

Note: See "Low-Power HCSL Outputs" table for slew rates.

SMBus Table: REF Control Register

Byte 3 Name Control Function Type 0 1 Default

Bit 7

RW 00 = Slowest 01 =Slow 0

Bit 6

RW 10 = Fast 11 = Fastest 1

Bit 5

REF Power Down Function Wake-on-Lan Enable for REF RW

REF disabled in

Power Down

REF runs in Power

Down

Bit 4

REF OE REF Output Enable RW

Disabled

Enabled 1

Bit 3

Bit 2

Bit 1

Bit 0

1. The disabled state depends on Byte11[1:0]. '00' = Low, '01'=HiZ, '10'=Low, '11'=HIgh

Byte 4 is Reserved

1. A low on these bits will overide the OE# pin and force the BCLKferential output to the state indicated by B11[1:0] (Low/Low default).

Reserved

00' = SS Off, '01' = -0.25% SS,

'10' = Reserved, '11'= -0.5% SS

00' for SS_EN_tri = 0, '01' for SS_EN_tri

= 'M', '11 for SS_EN_tri = '1'

Reserved

Controls Output Amplitude

Reserved

REF Slew Rate Control

Reserved

See B11[1:0]

Reserved

1. Spread must be selected OFF or ON with the hardware latch pin. These bits should not be used to turn spread ON or OFF after

power up. These bits can be used to change the spread amount, and B1[5] must be set to a 1 for these bits to have any effect on the

part. If These bits are used to turn spread OFF or ON, the system will need to be reset.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

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Description:

Clock Buffer 4 O/P CK420BQ Lite OEM

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