NOVEMBER 4, 2016 7 4-OUTPUT CK420BQ DERIVATIVE
9SQL4954 DATASHEET
Electrical Characteristics–BCLK Low-Power HCSL Outputs
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
g
in
g
on, fast settin
g
2.2 3.2 4.5
V/ns
2,3
Scope averaging, slow setting 1.5 2.3 3.5
V/ns
2,3
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 411 550 mV 1,4,5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 12 140 mV 1,4,9
Avg. Clock Period Accuracy
T
PERIOD_AVG
-50 0 +2550
ppm
2,10,13
Absolute Period
T
PERIOD_ABS
Includes jitter and Spread Spectrum Modulation 9.94906 10.0 10.1011
ns
2,6
Jitter, Cycle to cycle t
j
c
y
c-c
y
c
23 50 ps 2
Voltage High V
HIGH
660 770 850 1,15
Voltage Low V
LOW
-150 25 150 1,15
Absolute Max Voltage Vmax 822 1150 1,7,15
Absolute Min Voltage Vmin -300 -63 1,8,15
Duty Cycle t
DC
45 49 55 % 2
Slew rate matching
Δ
Trf 14 20
%
1,14
Skew, Output to Output t
sk3
Averaging on, V
T
= 50% 24 50 ps 2
2
Measured from differential waveform.
8
Defined as the minimum instantaneous voltage including undershoot.
15
At default SMBus amplitude settings.
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
Slew rate Trf
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
14
Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on the
median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-;
the maximum allowed difference should not exceed 20% of the slowest edge rate.
1
Measured from single-ended waveform.
3
Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic
through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
4
Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
5
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
6
Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread
spectrum modulation.
7
Defined as the maximum instantaneous volta
g
e includin
g
overshoot.
9
Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in
V
CROSS
for any particular system.
10
Refer to Section 4.3.7.1.1 of the PCI Express Base Specification, Revision 3.0 for information regarding PPM considerations.
11
System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL.
Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential
probe can be used for differential measurements. Test load CL = 2 pF.
12
T
STABLE
is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is allowed
to droo
p
back into the VRB ±100 mV differential ran
g
e.
13
PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly or
100 Hz. For 50 PPM, then we have an error budget of 100 Hz/PPM * 50 PPM = 5 kHz. The period is to be measured with a frequency counter
with measurement window set to 100 ms or greater. The ±50PPM applies to systems that do not employ Spread Spectrum Clocking, or that
use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500 PPM nominal shift in maximum
period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,550 PPM.
4-OUTPUT CK420BQ DERIVATIVE 8 NOVEMBER 4, 2016
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Electrical Characteristics–Phase Jitter Parameters - PCIe Common Clocked (CC)
Architectures
1, 2, 5
Electrical Characteristics–Phase Jitter Parameters - PCIe Independent Reference (IR)
Architectures
1, 5, 6
T
AMB
= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
SPECIFICATION
LIMIT
UNITS NOTES
t
jp
hPCIeG1-CC
PCIe Gen 1 17 30 86 ps (p-p) 3
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
0.4 0.6 3
ps
(rms)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
1.1
1.7 3.1
ps
(rms)
t
jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
0.29
0.42 1
ps
(rms)
t
jphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
0.29
0.42 0.5
ps
(rms)
Phase Jitter,
PLL Mode
t
jphPCIeG2-CC
T
AMB
= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX INDUSTRY LIMIT UNITS NOTES
t
jphPCIeG1-
SRIS
PCIe Gen 1 n/a None
ps
(rms)
2, 7
t
jphPCIeG2-
SRIS
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
0.8 1.2 2
ps
(rms)
2
t
jphPCIeG3-
SRIS
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.4
0.5
0.7
ps
(rms)
2
t
jphPCIeG4-
SRIS
PCIe Gen 4
(PLL BW of 2-4MHz, CDR = 10MHz)
n/a None
ps
(rms)
2, 7
Notes on PCIe Filter Phase Jitter Tables
1
Applies to all differential outputs,
g
uaranteed by desi
g
n and characterization.
5
Driven by 9FGL0841 or equivalent
6
IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock
architectures.
7
According to the PCIe Base Specification Rev4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter limits are not
defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this
table. There are no accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates
Phase Jitter, PLL
Mode
2
Based on PCIe Base Specification Rev4.0 version 0.7draft. See http://www.pcisi
g
.com for latest specifications.
3
Sample size of at least 100K cycles. This fi
g
ures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Additive jitter for RMS values is calculated by solvin
g
for b where [b=sqrt(
c
2
-
a
2
)], a is rms input jitter and c is rms total jitter.
NOVEMBER 4, 2016 9 4-OUTPUT CK420BQ DERIVATIVE
9SQL4954 DATASHEET
Electrical Characteristics–Filtered Phase Jitter Parameters - QPI/UPI, SAS
1, 2
Electrical Characteristics–12kHz-20MHz phase Jitter
Electrical Characteristics–Current Consumption
T
AMB
= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
SPECIFICATION
LIMIT
UNITS NOTES
QPI & UPI
(100MHz or 133MHz, 4.8Gb/s,
6.4Gb/s 12UI)
0.11 0.15 0.5
ps
(rms)
QPI & UPI
(100MHz, 8.0Gb/s, 12UI)
0.08 0.11 0.3
ps
(rms)
QPI & UPI
(100MHz,
?
9.6Gb/s, 12UI)
0.07 0.1 0.2
ps
(rms)
Phase Jitter,
SAS12G
BCLK Outputs
t
jphSAS12G
100MHz, SSC Off,
REF output enabled
0.40 0.45 1.2
ps
(rms)
1,2
Notes
1
Applies to all differential outputs, guaranteed by design and characterization.
Phase Jitter, PLL
Mode
t
jphQPI_UPI
2
Calculated from Intel-supplied Clock Jitter Tool
3
For RMS values additive jitter is calculated by solving for b where [b=sqrt(c
2
-a
2
) ], a is rms input jitter and c is rms total jitter.
T
AMB
= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
SPECIFICATION
LIMIT
UNITS NOTES
Phase Jitter,
12kHz-20MHz
BCLK Outputs
t
jph12k-20M
100MHz, SSC Off,
REF output enabled
1.5 2 n/a
ps
(rms)
1
Notes
1
Applies to all differential outputs, guaranteed by design and characterization.
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DDAOP
VDDA, All outputs active @100MHz 13 16 mA
I
DDOP
All other VDD, except VDDA, All outputs active
@100MHz
30 40 mA
I
DDAP
D
VDDA, BCLK outputs off, REF output on 0.7 1 mA 1
I
DDPD
All other VDD, except VDDA,
BCLK outputs off, REF output running
912mA1
I
DDAPD
VDDA, all outputs off 0.7 1 mA
I
DDPD
All other VDD, except VDDA, all outputs off 5 9 mA
1
This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Operating Supply Current
Wake-on-LAN Current
(Power down state and
Byte 3, bit 5 = '1')
Powerdown Current
(Power down state and
Byte 3, bit 5 = '0')

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Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 4 O/P CK420BQ Lite OEM
Lifecycle:
New from this manufacturer.
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