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LT1952EGN-1#TRPBF

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LT1952/LT1952-1
10
19521fe
TIMING DIAGRAM
BLOCK DIAGRAM
1952 F01
t
DELAY
: PROGRAMMABLE SYNCHRONOUS DELAY
FAULTS TRIGGERING SOFT-START
V
IN
< 8.75V
OR
SD_V
SEC
< 1.32V (UVLO)
OR
OC > 107mV (OVERCURRENT)
SOFT-START LATCH RESET:
V
IN
> 14.25V (> 8.75V IF LATCH SET BY OC)
AND
SD_V
SEC
> 1.32V
AND
OC < 107mV
AND
SS_MAXDC < 0.45V
SOFT-START
LATCH SET
SOUT
OUT
SS_MAXDC
0.8V (ACTIVE THRESHOLD)
0.45V (RESET THRESHOLD)
0.2V
V
REF
>90%
–
+
–
+
+
–
SOURCE
2.5mA
2.5V
1.23V
(100 TO 500)kHz
OSC
(TYPICAL 200kHz)
I
HYST
10µA SD_V
SEC
= 1.32V
0µA SD_V
SEC
> 1.32V
7
5
14
13
6
3
4
10
81 92
SD_V
SEC
R
OSC
SYNC
1.32V
1.23V
ADAPTIVE
MAXIMUM
DUTY CYCLE
CLAMP
(LINEAR)
SLOPE COMP
8µA 0% DC
35µA 80% DC
RAMP
S
Q
R
R
Q
S
BLANK
FB COMP GND BLANK
12
DELAY
V
REF
15
V
IN
SS_MAXDC
SOFT-START CONTROL
OUT
16
SOUT
PGND
I
SENSE
11
OC
DRIVER
±1A
±50mA
12V
13V
0.45V
1952 BD
–
+
–
+
(VOLTAGE)
ERROR AMPLIFIER
107mV
0mV TO 220mV
ON
DELAY
V
IN
ON
V
IN
OFF
LT1952
I
START
= 460µA
V
IN
ON = 14.25V
V
IN
OFF = 8.75V
LT1952-1
I
START
= 400µA
V
IN
ON = 7.75V
V
IN
OFF = 6.5V
START-UP
INPUT CURRENT (ISTART)
–
+
+
–
SENSE
CURRENT
+
–
OVER
CURRENT
Figure 1. Timing Diagram
Figure 2. Block Diagram
LT1952/LT1952-1
11
19521fe
OPERATION
Introduction
The LT1952/LT1952-1 are current mode synchronous
PWM controllers optimized for control of the simplest
forward converter topology—using only one primary
MOSFET. The LT1952/LT1952-1 are ideal for 25W to 500W
power systems where very high efficiency and reliability,
low complexity and cost are required in a small space.
Key features of the LT1952/LT1952-1 include an adaptive
maximum duty cycle clamp for the single primary MOSFET.
An additional output signal is included for synchronous
rectifier control. A precision 107mV threshold senses
overcurrent conditions and triggers Soft-Start for low
stress short-circuit protection and control. The key
functions of the LT1952/LT1952-1 are shown in the Block
Diagram in Figure 2.
Part Start-up
In normal operation the SD_V
SEC
pin must exceed 1.32V
and the V
IN
pin must exceed 14.25V (7.75V LT1952-1) to
allow the part to turn on. This combination of pin voltages
allows the 2.5V V
REF
pin to become active, supplying the
LT1952/LT1952-1 control circuitry and providing up to
2.5mA external drive. SD_V
SEC
threshold can be used for
externally programming an undervoltage lockout (UVLO)
threshold on the system input voltage. Hysteresis on
the UVLO threshold can also be programmed since the
SD_V
SEC
pin draws 11µA just before part turn on and 0µA
after part turn on.
With the LT1952/LT1952-1 turned on, the V
IN
pin can drop
as low as 8.75V (6.5V LT1952-1) before part shutdown
occurs. This V
IN
pin hysteresis (5.5V LT1952; 1.25V
LT1952-1) combined with low 460µA (400µA LT1952-1)
start-up input current allows low power start-up using
a resistor/capacitor network from system V
IN
to supply
the V
IN
pin (Figure 3). The V
IN
capacitor value is chosen
to prevent V
IN
falling below its turn off threshold before
an auxiliary winding in the converter takes over supply
to the V
IN
pin.
Output Drivers
The LT1952/LT1952-1 have two outputs, SOUT and OUT.
The OUT pin provides a ±1A peak MOSFET gate drive
clamped to 13V. The SOUT pin has a ±50mA peak drive
clamped to 12V and provides sync signal timing for syn-
chronous rectification control.
For SOUT and OUT turn on, a PWM latch is set at the start
of each main oscillator cycle. OUT turn on is delayed from
SOUT turn on by a time t
DELAY
(Figure 2). t
DELAY
is pro-
grammed using a resistor from the DELAY pin to ground
and is used to set the timing control of the secondary
synchronous rectifiers for optimum efficiency.
SOUT and OUT turn off at the same time each cycle by
one of three methods:
(1) MOSFET peak current sense at I
SENSE
pin
(2) Adaptive maximum duty cycle clamp reached during
load/line transients
(3) Maximum duty cycle reset of the PWM latch
During any of the following conditions—low V
IN
, low
SD_V
SEC
or overcurrent detection at the OC pin—a soft-
start event is latched and both SOUT and OUT turn off
immediately (Figure 1).
Leading Edge Blanking
To prevent MOSFET switching noise causing premature turn
off of SOUT or OUT, programmable leading edge blanking
exists. This means both the current sense comparator
and overcurrent comparator outputs are ignored during
MOSFET turn on and for an extended period after the OUT
leading edge (Figure 6). The extended blanking period is
programmable by adjusting a resistor from the BLANK
pin to ground.
Adaptive Maximum Duty Cycle Clamp
(Volt-Second Clamp)
For forward converter applications using the simplest
topology of a single MOSFET on the primary, a maximum
switch duty cycle clamp which adapts to transformer input
voltage is necessary for reliable control of the MOSFET. This
volt-second clamp provides a safeguard for transformer
reset that prevents transformer saturation. Instantaneous
load changes can cause the converter loop to demand
maximum duty cycle. If the maximum duty cycle of the
switch is too great, the transformer reset voltage can
exceed the voltage rating of the primary-side MOSFET with
LT1952/LT1952-1
12
19521fe
OPERATION
catastrophic damage. Many converters solve this problem
by limiting the operational duty cycle of the MOSFET to
50% or less—or by using a fixed (non-adaptive) maximum
duty cycle clamp with very large voltage rated MOSFETs.
The LT1952/LT1952-1 provide a volt-second clamp to
allow MOSFET duty cycles well above 50%. This gives
greater power utilization for the MOSFET, rectifiers and
transformer resulting in less space for a given power
output. In addition, the volt-second clamp allows a reduced
voltage rating on the MOSFET resulting in lower RDS
ON
for greater efficiency. The volt-second clamp defines a
maximum duty cycle ‘guard rail’ which falls when system
input voltage increases.
The LT1952/LT1952-1 SD_V
SEC
and SS_MAXDC pins
provide a capacitorless, programmable volt-second clamp
solution. Some controllers with volt-second clamps control
switch maximum duty cycle by using an external capacitor
to program maximum switch ON time. Such techniques
have a volt-second clamp inaccuracy directly related to
the error of the external capacitor/pin capacitance and the
error/drift of the internal oscillator. The LT1952/LT1952-
1 use simple resistor ratios to implement a volt-second
clamp without the need for an accurate external capacitor
and with an order of magnitude less dependency on
oscillator error.
An increase of voltage at the SD_V
SEC
pin causes the
maximum duty cycle clamp to decrease. If SD_V
SEC
is
resistively divided down from transformer input voltage,
a volt-second clamp is realised. To adjust the initial
maximum duty cycle clamp, the SS_MAXDC pin voltage
is programmed by a resistor divider from the 2.5V V
REF
pin to ground. An increase of programmed voltage on
SS_MAXDC pin provides an increase of switch maximum
duty cycle clamp.
Soft-Start
The LT1952/LT1952-1 provide true PWM soft-start by
using the SS_MAXDC pin to control soft-start timing. The
proportional relationship between SS_MAXDC voltage and
switch maximum duty cycle clamp allows the SS_MAXDC
pin to slowly ramp output voltage by ramping the maximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
A soft-start event is triggered whenever V
IN
is too low,
SD_V
SEC
is too low (UVLO), or a 107mV overcurrent
threshold at OC pin is exceeded. Whenever a soft-start
event is triggered, switching at SOUT and OUT is stopped
immediately.
The SS_MAXDC pin is discharged and only released for
charging when it has fallen below it’s reset threshold
of 0.45V and all faults have been removed. Increasing
voltage on the SS_MAXDC pin above 0.8V will increase
switch maximum duty cycle. A capacitor to ground on
the SS_MAXDC pin in combination with a resistor divider
from V
REF
, defines the soft-start timing.
Current Mode Topology (I
SENSE
Pin)
The LT1952/LT1952-1 current mode topology eases fre-
quency compensation requirements because the output
inductor does not contribute to phase delay in the regulator
loop. This current mode technique means that the error
amplifier (nonisolated applications) or the optocoupler
(isolated applications) commands current (rather than
voltage) to be delivered to the output. This makes frequency
compensation easier and provides faster loop response
to output load transients.
A resistor divider from the application’s output voltage
generates a voltage at the inverting FB input of the LT1952/
LT1952-1 error amplifier (or to the input of an external
optocoupler) and is compared to an accurate reference
(1.23V for LT1952/LT1952-1). The error amplifier output
(COMP) defines the input threshold (I
SENSE
) of the current
sense comparator. COMP voltages between 0.8V (active
threshold) and 2.5V define a maximum I
SENSE
threshold
from 0mV to 220mV. By connecting I
SENSE
to a sense
resistor in series with the source of an external power
MOSFET, the MOSFET peak current trip point (turn off)
can be controlled by COMP level and hence by the output
voltage. An increase in output load current causing the
output voltage to fall, will cause COMP to rise, increasing
I
SENSE
threshold, increasing the current delivered to the
output. For isolated applications, the error amplifier COMP
output can be disabled to allow the optocoupler to take
control. Setting FB = V
REF
disables the error amplifier COMP
output, reducing pin current to (COMP – 0.7)/40k.
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LT1952EGN-1#TRPBF

Mfr. #:
Buy LT1952EGN-1#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1x Switch Sync For Cntr
Lifecycle:
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