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PCK9456BD,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
1. General description
The PCK9456 is a 2.5 V and 3.3 V compatible 1 : 10 clock distribution buffer designed for
low voltage mid-range to high-performance telecommunications, networking and
computing applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for
mixed voltage applications. The PCK9456 offers 10 low-skew outputs and a differential
LVPECL clock input. The outputs are configurable and support 1 : 1 and 1 : 2 output to
input frequency ratios. The PCK9456 is specified for the extended temperature range of
−40 °C to +85 °C.
2. Features
n Configurable 10 outputs LVCMOS clock distribution buffer
n Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply
n Wide range output clock frequency up to 250 MHz
n Designed for mid-range to high performance telecommunications, networking and
computer applications
n Supports high performance differential clocking applications
n Maximum output skew of 200 ps (150 ps within one bank)
n Selectable output configurations per output bank
n 3-stateable outputs
n Available in LQFP32 package
n Ambient operating temperature of −40 °C to +85 °C
3. Ordering information
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
Rev. 01 — 31 July 2006 Product data sheet
Table 1. Ordering information
Type number Package
Name Description Version
PCK9456BD LQFP32 plastic low profile quad flat package; 32 leads;
body 7 × 7 × 1.4 mm
SOT358-1
PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 31 July 2006 2 of 18
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
4. Functional diagram
Fig 1. Functional diagram of PCK9456
002aab862
QA0
QA1
PCLK
PCLK
PCK9456
CLK
CLK ÷ 2
QA2
bank A
0
1
25 kΩ
25 kΩ
0.5V
CC
QB0
QB1
QB2
bank B
QC0
QC1
QC2
bank C
QC3
FSELA
25 kΩ
FSELB
25 kΩ
FSELC
25 kΩ
MR/OE
25 kΩ
0
1
0
1
PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 31 July 2006 3 of 18
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 2. Pin configuration for LQFP32
PCK9456BD
n.c. GND
V
CC
QB0
PECL_CLK VCCB
PECL_CLK QB1
FSELA GND
FSELB QB2
FSELC VCCB
GND VCCC
VCCC MR/OE
QC0 GND
GND QA0
QC1 VCCA
VCCC QA1
QC2 GND
GND QA2
QC3 VCCA
002aab863
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
Table 2. Pin description
Symbol Pin Type Description
PECL_CLK 3 LVPECL differential clock reference
low voltage positive ECL input
PECL_CLK 4 LVPECL
FSELA 5 LVCMOS output bank divide select input
FSELB 6 LVCMOS
FSELC 7 LVCMOS
GND 8, 11, 15, 20,
24, 27, 31
supply ground
VCCA 25, 29 supply positive voltage supply for output bank A
VCCB 18, 22 supply positive voltage supply for output bank B;
internally connected to V
CC
VCCC 9, 13, 17 supply positive voltage supply for output bank C
V
CC
2 supply positive voltage supply core (V
CC
)
QA0, QA1, QA2 30, 28, 26 LVCMOS bank A outputs
QB0, QB1, QB2 23, 21, 19 LVCMOS bank B outputs
QC0, QC1, QC2, QC3 10, 12, 14, 16 LVCMOS bank C outputs
MR/
OE 32 LVCMOS internal reset and output 3-state control
n.c. 1 - not connected
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

PCK9456BD,151

Mfr. #:
Buy PCK9456BD,151
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 1:10 250MHZ 32LQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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