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PCK9456BD,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 31 July 2006 4 of 18
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
6. Functional description
The PCK9456 is a full static design supporting clock frequencies up to 250 MHz. The
signals are generated and re-timed on-chip to ensure minimal skew between the three
output banks (see Figure 1 “Functional diagram of PCK9456”).
Each of the three output banks can be individually supplied by 2.5 V or 3.3 V, supporting
mixed voltage applications. The FSELx pins choose between division of the input
reference frequency by one or two. The frequency divider can be set individually for each
of the three output banks. The PCK9456 can be reset and the outputs are disabled by
deasserting the MR/OE pin (logic HIGH state). Asserting MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50 Ω transmission lines. The clock input is
low voltage PECL compatible for differential clock distribution support. Please consult the
PCK9446 specification for a full CMOS compatible device. For series terminated
transmission lines, each of the PCK9456 outputs can drive one or two traces, giving the
devices an effective fan-out of 1 : 20. The device is packaged in a 7 mm × 7 mm LQFP32
package.
Table 3 details the supported single and dual supply configurations.
[1] V
CC
is the positive power supply of the device core and input circuitry. V
CC
voltage defines the input
threshold and levels.
[2] V
CC(bankA)
is the positive power supply of the bank A outputs. V
CC(bankA)
voltage defines bank A output
levels.
[3] V
CC(bankB)
is the positive power supply of the bank B outputs. V
CC(bankB)
voltage defines the bank B output
levels. V
CC(bankB)
is internally connected to V
CC
.
[4] V
CC(bankC)
is the positive power supply of the bank C outputs. V
CC(bankC)
voltage defines bank C output
levels.
6.1 Function table
Table 3. Supported single and dual supply configurations
Supply voltage
configuration
V
CC
[1]
V
CC(bankA)
[2]
V
CC(bankB)
[3]
V
CC(bankC)
[4]
GND
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 0 V
Mixed voltage supply 3.3 V 3.3 V or 2.5 V 3.3 V 3.3 V or 2.5 V 0 V
2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 0 V
Table 4. Function table (controls)
Control Default 0 1
FSELA 0 QA[0:2] frequency = f
ref
QA[0:2] frequency = f
ref
÷ 2
FSELB 0 QB[0:2] frequency = f
ref
QB[0:2] frequency = f
ref
÷ 2
FSELC 0 QC[0:3] frequency = f
ref
QC[0:3] frequency = f
ref
÷ 2
MR/
OE 0 outputs enabled internal reset; outputs disabled (3-state)
PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 31 July 2006 5 of 18
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
7. Limiting values
8. Recommended operating conditions
9. Characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage −0.3 +4.6 V
V
I
input voltage −0.3 V
CC
+ 0.3 V
V
O
output voltage −0.3 V
CC
+ 0.3 V
I
I
input current - ±20 mA
I
O
output current - ±50 mA
T
stg
storage temperature −40 +125 °C
Table 6. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
V
CC
supply voltage 2.375 - 3.465 V
V
CC(bankA)
supply voltage (bank A) VCCA pins 2.375 - 3.465 V
V
CC(bankB)
supply voltage (bank B) VCCB pins 2.375 - 3.465 V
V
CC(bankC)
supply voltage (bank C) VCCC pins 2.375 - 3.465 V
T
amb
ambient temperature −40 - +85 °C
Table 7. General characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
T
termination voltage output - 0.5V
CC
-V
V
esd
electrostatic discharge
voltage
MM 200 - - V
HBM 2000 - - V
I
latch(prot)
latch-up protection current 200 - - mA
C
PD
power dissipation
capacitance
per output - 10 - pF
C
i
input capacitance - 4.0 - pF
PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 31 July 2006 6 of 18
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
[1] V
ICR
(DC) is the crossing point of the differential input signal. Functional operation is obtained when the crossing point is within the V
ICR
range and the input swing lies within the V
i(p-p)
(DC) specification.
[2] Input pull-up/pull-down resistors influence input current.
[3] The PCK9456 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of V
T
. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
[4] I
CC(max)
is the DC current consumption of the device with all outputs open and the input in its default state or open.
[1] V
ICR
(DC) is the crossing point of the differential input signal. Functional operation is obtained when the crossing point is within the V
ICR
range and the input swing lies within the V
i(p-p)
(DC) specification.
[2] Input pull-up/pull-down resistors influence input current.
[3] The PCK9456 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated
transmission line to a termination voltage of V
T
. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
[4] I
CC(max)
is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 8. Static characteristics (3.3 V)
T
amb
=
−
40
°
C to +85
°
C; V
CC
=V
CC(bankA)
=V
CC(bankB)
=V
CC(bankC)
= 3.3 V
±
5%
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage LVCMOS 2.0 - V
CC
+ 0.3 V
V
IL
LOW-level input voltage LVCMOS −0.3 - +0.8 V
V
i(p-p)
peak-to-peak input voltage PCLK; LVPECL 250 - - V
V
ICR
common mode input voltage range PCLK; LVPECL
[1]
1.1 - V
CC
− 0.6 V
I
I
input current V
I
= GND or V
I
=V
CC
[2]
-- ±200 µA
V
OH
HIGH-level output voltage I
OH
= −24 mA
[3]
2.4 - - V
V
OL
LOW-level output voltage I
OL
=24mA
[2]
- - 0.55 V
I
OL
= 12 mA - - 0.30
Z
o
output impedance - 14 to 17 - Ω
I
CC(max)
maximum supply current all V
CC
pins
[4]
- - 2.0 mA
Table 9. Static characteristics (2.5 V)
T
amb
=
−
40
°
C to +85
°
C; V
CC
=V
CC(bankA)
=V
CC(bankB)
=V
CC(bankC)
= 2.5 V
±
5%
Symbol Parameter Conditions Min Typ Max Unit
V
IH
HIGH-level input voltage LVCMOS 1.7 - V
CC
+ 0.3 V
V
IL
LOW-level input voltage LVCMOS −0.3 - +0.7 V
V
i(p-p)
peak-to-peak input voltage PCLK; LVPECL 250 - - V
V
ICR
common mode input voltage range PCLK; LVPECL
[1]
1.1 - V
CC
− 0.7 V
I
I
input current V
I
= GND or V
I
=V
CC
[2]
-- ±200 µA
V
OH
HIGH-level output voltage I
OH
= −15 mA
[3]
1.8 - - V
V
OL
LOW-level output voltage I
OL
=15mA
[2]
- - 0.6 V
Z
o
output impedance - 17 to 20 - Ω
I
CC(max)
maximum supply current all V
CC
pins
[4]
- - 2.0 mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

PCK9456BD,151

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Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 1:10 250MHZ 32LQFP
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