PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 31 July 2006 7 of 18
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
[1] Dynamic (AC) characteristics apply for parallel output termination of 50 Ω to V
T
.
[2] The PCK9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
[3] V
ICR
(AC) is the crossing point of the differential input signal. Normal AC operation is obtained when the crossing point is within the V
ICR
range and the input swing lies within the V
i(p-p)
(AC) specification.
[4] Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, part-to-part skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
[5] Output disable time.
[6] Output enable time.
[7] Output pulse skew is the absolute difference of the propagation delay times: |t
PLH
− t
PHL
|.
Table 10. Dynamic characteristics (3.3 V)
T
amb
=
−
40
°
C to +85
°
C; V
CC
=V
CC(bankA)
=V
CC(bankB)
=V
CC(bankC)
= 3.3 V
±
5%
[1]
Symbol Parameter Conditions Min Typ Max Unit
f
i
input frequency
[2]
0 - 250 MHz
f
o(max)
maximum output frequency divide-by-1 output;
FSELx = 0
[2]
0 - 250 MHz
divide-by-2 output;
FSELx = 1
0 - 125 MHz
V
i(p-p)
peak-to-peak input voltage PCLK; LVPECL 500 - 1000 mV
V
ICR
[3]
common mode input voltage range PCLK; LVPECL 1.3 - V
CC
− 0.8 V
t
p(i)(ref)
reference input pulse duration 1.4 - - ns
t
r
rise time PCLK input;
0.8 V to 2.0 V
- - 1.0
[4]
ns
t
f
fall time PCLK input;
2.0 V to 0.8 V
- - 1.0
[4]
ns
t
PLH
LOW-to-HIGH propagation delay CCLK to any Q 2.2 2.8 4.45 ns
t
PHL
HIGH-to-LOW propagation delay CCLK to any Q 2.2 2.8 4.2 ns
t
PLZ
LOW to OFF-state propagation delay
[5]
- - 10 ns
t
PHZ
HIGH to OFF-state propagation delay
[5]
- - 10 ns
t
PZL
OFF-state to LOW propagation delay
[6]
- - 10 ns
t
PZH
OFF-state to HIGH propagation delay
[6]
- - 10 ns
t
sk(o)
output skew time output-to-output
within one bank - - 150 ps
any output bank,
same output divider
- - 200 ps
any output,
any output divider
- - 1.0 ns
t
sk(pr)
process skew time part-to-part - - 1.0 ns
t
sk(p)
pulse skew time output
[7]
- - 500 ps
δ
o
output duty cycle divide-by-1 output;
δ
ref
=50%
47 50 62.5 %
divide-by-2 output;
δ
ref
= 25 % to 75 %
45 50 55 %
t
r
rise time output; 0.55 V to 2.4 V 0.2 - 1.0 ns
t
f
fall time output; 2.4 V to 0.55 V 0.2 - 1.0 ns
