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PCK9456BD,151

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 31 July 2006 10 of 18
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
10. Application information
10.1 Driving transmission lines
The PCK9456 clock driver was designed to drive high speed signals in a terminated
transmission line environment. To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance possible. With an output
impedance of less than 20 Ω, the drivers can drive either parallel or series terminated
transmission lines.
In most high performance clock networks, point-to-point distribution of signals is the
method of choice. In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel technique terminates the signal at
the end of the line with a 50 Ω resistance to 0.5V
CC
. This technique draws a fairly high
level of DC current, and thus only a single terminated line can be driven by each output of
the PCK9456 clock driver. For the series terminated case, however, there is no DC current
draw, thus the outputs can drive multiple series terminated lines. Figure 7 illustrates an
output driving a single series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fan-out of the PCK9456 clock driver is effectively doubled
due to its capability to drive multiple lines.
Fig 7. Single versus dual transmission lines
Z
o
= 50 Ω
002aab864
R
s
= 36 Ω
Z
o
= 50 Ω
R
s
= 36 Ω
PCK9456
OUTPUT
BUFFER
OutB1
OutB0
14 Ω
Z
o
= 50 Ω
R
s
= 36 Ω
PCK9456
OUTPUT
BUFFER
OutA
14 Ω
IN
IN
R
o
R
o
PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 31 July 2006 11 of 18
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
The waveform plots of Figure 8 show simulation results of an output driving a single line
versus two lines. In both cases the drive capability of the PCK9456 output buffer is more
than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay
measurement in the simulations a delta of only 43 ps exists between the two differently
loaded outputs. This suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the PCK9456. The output waveform in Figure 8
shows a step in the waveform; this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36 Ω series resistor plus the output
impedance does not match the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
where:
Z
o
=50Ω||50 Ω
R
s
=36Ω||36 Ω
R
o
=14Ω
At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V.
It will then increment towards the quiescent 3.0 V in steps separated by one round trip
delay (in this case 4.0 ns).
Since this step is well above the threshold region it will not cause any false clock
triggering, however designers may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multiple lines, the situation in Figure 9
should be used. In this case the series terminating resistors are reduced such that when
the parallel combination is added to the output buffer impedance the line impedance is
perfectly matched.
Fig 8. Single versus dual line termination waveforms
V
L
V
S
Z
o
R
s
R
o
Z
o
++
------------------------------


=
V
L
3.0
25
18 14 25++
------------------------------


1.31 V==
time (ns)
0161248
002aab874
3.0
voltage
(V)
−0.5
0
1.0
2.0
IN
OutA
t
d
= 3.8956 ns
OutB
t
d
= 3.9386 ns
PCK9456_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 01 — 31 July 2006 12 of 18
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
11. Test information
14 Ω +22Ω||22 Ω =50Ω||50 Ω
25 Ω =25Ω
Fig 9. Optimized dual line termination
Z
o
= 50 Ω
002aab865
R
s
= 22 Ω
Z
o
= 50 Ω
R
s
= 22 Ω
PCK9456
OUTPUT
BUFFER
14 Ω
IN
R
o
Fig 10. PCLK PCK9456 AC test reference for V
CC
= 3.3 V and V
CC
= 2.5 V
Z
o
= 50 Ω
002aab866
R
T
= 50 Ω
V
T
Z
o
= 50 Ω
R
T
= 50 Ω
V
T
DIFFERENTIAL
PULSE
GENERATOR
Z = 50 Ω
PCK9456
D.U.T.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

PCK9456BD,151

Mfr. #:
Buy PCK9456BD,151
Manufacturer:
NXP Semiconductors
Description:
IC CLK BUFFER 1:10 250MHZ 32LQFP
Lifecycle:
New from this manufacturer.
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