IS42/45SM/RM/VM16800G
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Rev. A | Apr. 2012
2M x 16Bits x 4Banks Mobile Synchronous DRAM
Description
These IS42/45SM/RM/VM16800G are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 2,097,152 words x 16
bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
JEDEC standard 3.3V, 2.5V, 1.8V power supply
Auto refresh and self refresh
All pins are compatible with LVCMOS interface
4K refresh cycle / 64ms
Programmable Burst Length and Burst Type
1, 2, 4, 8 or Full Page for Sequential Burst
4 or 8 for Interleave Burst
Programmable CAS Latency : 2,3 clocks
All inputs and outputs referenced to the positive edge of the
system clock
Data mask function by DQM
Internal 4 banks operation
Burst Read Single Write operation
Special Function Support
PASR(Partial Array Self Refresh)
Auto TCSR(Temperature Compensated Self Refresh)
Programmable Driver Strength Control
Full Strength or 1/2, 1/4, 1/8 of Full Strength
Deep Power Down Mode
Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge
Features
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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www.issi.com - DRAM@issi.com
Rev. A | Apr. 2012
IS42/45SM/RM/VM16800G
Figure1: 54Ball FBGA Ball Assignment
[Top View]
A
B
C
D
E
F
G
H
J
1 2 3 4 5 6 7 8 9
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
UDQM CLK CKE
NC A11 A9
A8 A7 A6
VSS A5 A4
VDDQ DQ0 VDD
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
VSSQ DQ6 DQ5
/CAS /RAS /WE
BA0 BA1 /CS
A0 A1 A10
A3 A2 VDD
DQ8 NC VSS VDD LDQM DQ7
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Rev. A | Apr. 2012
IS42/45SM/RM/VM16800G
Table2: Pin Descriptions
Pin Pin Name Descriptions
CLK System Clock
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK.
CKE Clock Enable
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
/CS Chip Select Enable or disable all inputs except CLK, CKE and DQM.
BA0~BA1 Bank Address
Selects bank to be activated during RAS activity.
Selects bank to be read/written during CAS activity.
A0~A11 Address
Row Address : RA0~RA11
Column Address : CA0~CA8
Auto Precharge : A10
/RAS, /CAS, /WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation.
Refer function truth table for details.
LDQM,UDQM Data Input/Output Mask
Controls output buffers in read mode and masks input data in
write mode.
DQ0~DQ15 Data Input/Output Data input/output pin.
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC No Connection No connection.

IS42RM16800G-75BLI-TR

Mfr. #:
Manufacturer:
Description:
DRAM 128M (8Mx16) 133MHz Mobile SDRAM, 2.5v
Lifecycle:
New from this manufacturer.
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