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IS42RM16800G-75BLI-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
16
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Rev. A | Apr. 2012
IS42/45SM/RM/VM16800G
Note :
1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge.
2. All entries assume that CKE was active during the preceding clock cycle.
3. If both banks are idle and CKE is inactive, then in power down cycle
4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address,
depending on the state of that bank.
5. If both banks are idle and CKE is inactive, then Self Refresh mode.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. Must satisfy burst interrupt condition.
9. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10. Must mask preceding data which don't satisfy tDPL.
11. Illegal if tRRD is not satisfied
12. Illegal for single bank, but legal for other banks in multi-bank devices.
13. Illegal for all banks.
14. Mode Register Set and Extended Mode Register Set is same command truth table except BA.
17
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Rev. A | Apr. 2012
IS42/45SM/RM/VM16800G
Table6: CKE Truth Table
Current
State
CKE Command
Action Note
Prev
Cycle
Current
Cycle
/CS /RAS /CAS /WE BA A0-A11
Self
Refresh
H X X X X X X X INVALID 2
L H H X X X X X
Exit Self Refresh with Device
Deselect
3
L H L H H H X
X Exit Self Refresh with No
Operation
3
L H L H H L X X ILLEGAL 3
L H L H L X X X ILLEGAL 3
L H L L X X X X ILLEGAL 3
L L X X X X X X Maintain Self Refresh
Power
Down
H X X X X X X X INVALID 2
L H
H X
X X X X Power Down Mode Exit, All
Banks Idle
3
L H H H X X
L H L
L X X X X
ILLEGAL
3
X L X X X
X X L X X
L L X X X X X X Maintain Power Down Mode
Deep
Power
Down
H X X X X X X X INVALID 2
L H X X X X X X Deep Power Down Mode Exit 6
L L X X X X X X Maintain Deep Power Down
Mode
All
Banks
Idle
H H H X X X Refer to the Idle State
section of the Current State
Truth Table
4
H H L H X X 4
H H L L H X 4
H H L L
L H X X Auto Refresh
H H L L L L OP CODE Mode Register Set 5
H L H X X X Refer to the Idle State
section of the Current State
Truth Table
4
H L L H X X 4
H L L L H X 4
H L L L L H X X Entry Self Refresh 5
H L L L L L OP CODE Mode Register Set
L X X X X X X X Power Down 5
Any
State
other
than
listed
above
H H X X X X X X Refer to Operations of the
Current State Truth Table
H L X X X X X X Begin Clock Suspend next
cycle
L H X X X X X X Exit Clock Suspend next
cycle
L L X X X X
X X Maintain Clock Suspend
18
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Rev. A | Apr. 2012
IS42/45SM/RM/VM16800G
Note :
1. H: Logic High, L: Logic Low, X: Don't care
2. For the given current state CKE must be low in the previous cycle.
3. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
4. The address inputs depend on the command that is issued.
5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state.
6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes
high and is maintained for a minimum 100usec.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

IS42RM16800G-75BLI-TR

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Description:
DRAM 128M (8Mx16) 133MHz Mobile SDRAM, 2.5v
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