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Rev. A | Apr. 2012
IS42/45SM/RM/VM16800G
WB
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table 3.
Table 3: Burst Definition
M9 Write Burst Mode
0 Burst Read and Burst Write
1 Burst Read and Single Write
M3 Burst Type
0 Sequential
1 Interleave
M6 M5 M4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
M2 M1 M0
Burst Length
M3 = 0 M3 = 1
0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
Burst
Length
Starting Column
Address
Order of Access Within a Burst
Sequential Interleaved
A2 A1 A0
2
0 0-1 0-1
1 1-0 1-0
4
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0
1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1
3-0-1-2 3-2-1-0
8
0 0 0
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1 0 1
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full
Page
n=A0-8
(Location 0-511)
C
n
, C
n
+1. C
n
+2,
C
n
+3, C
n
+4…
…C
n
-1, C
n
...
Not Supported
Note :
1. For full-page accesses: y = 512
2. For a burst length of two, A1-A8 select the block-
of-two burst; A0 selects the starting column within the
block.
3. For a burst length of four, A2-A8 select the block-
of-four burst; A0-A1 select the starting column within
the block.
4. For a burst length of eight, A3-A8 select the
block-of-eight burst; A0-A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0-A8
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0-A8 select the unique
column to be accessed, and mode register bit M3 is
ignored.
0 CAS Latency BT Burst Length
Address Bus
0 1 2 3 4 5 6 10 9 8 7 11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Mode Register (Mx)
0 0
0
Figure4: Mode Register Definition
Note: M13(BA1) and M12 (BA0) must be set to “0” to select Mode Register (vs. the Extended Mode Register)
BA0
BA1
0
12
13
0
