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IS42/45SM/RM/VM16800G
Table12: AC Characteristic (AC operation conditions unless otherwise noted)
Parameter Sym
-6 -75
Unit Note
Min Max Min Max
CLK Cycle Time
CL = 3 tCK3 6.0
1000
7.5
1000
ns
1
CL = 2 tCK2 10 10
Access time from CLK (pos. edge)
CL = 3 tAC3 5.5 6
2
CL = 2 tAC2 8 8
CLK High-Level Width tCH 2.5 2.5 3
CLK Low-Level Width tCL 2.5 2.5 3
CKE Setup Time tCKS 1.5 2.0
CKE Hold Time tCKH 1.0 1.0
/CS, /RAS, /CAS, /WE, DQM Setup Time tCMS 1.5 2.0
/CS, /RAS, /CAS, /WE, DQM Hold Time tCMH 1.0 1.0
Address Setup Time tAS 1.5 2.0
Address Hold Time tAH 1.0 1.0
Data-In Setup Time tDS 1.5 2.0
Data-In Hold Time tDH 1.0 1.0
Data-Out High-Impedance Time
from CLK (pos.edge)
CL = 3 tHZ3 5.5 6
4
CL = 2 tHZ2 8 8
Data-Out Low-Impedance Time tLZ 1.0 1.0
Data-Out Hold Time (load) tOH 2.5 2.5
Data-Out Hold Time (no load) tOHN
1.8 1.8
ACTIVE to PRECHARGE command tRAS 42 100K 45 100K
PRECHARGE command period tRP 18 19
ACTIVE bank a to ACTIVE bank a command tRC 60 67.5 5
ACTIVE bank a to ACTIVE bank b command tRRD 12 15
ACTIVE to READ or WRITE delay tRCD 18 19
READ/WRITE command to READ/WRITE
command
tCCD 1 1
CLK
6
WRITE command to input data delay tDWD 0 0 6
Data-in to PRECHARGE command tDPL 12 15
ns
7
Data-in to ACTIVE command tDAL 30 37.5 7
DQM to data high-impedance during READs tDQZ 2 2
CLK
6
DQM to data mask during WRITEs tDQM 0 0 6
LOAD MODE REGISTER command to ACTIVE
or REFRESH command
tMRD 2 2 8
Data-out to high-impedance from
PRECHARGE command
CL = 3 tROH3 3 3
6
CL = 2 tROH2 2 2
Last data-in to burst STOP command tBDL 1 1 6
Last data-in to new READ/WRITE command tCDL 1 1 6
CKE to clock disable or power-down entry
mode
tCKED 1 1
CLK
9
CKE to clock enable or power-down exit
setup mode
tPED 1 1 9
Refresh period (4,096 rows)
tREF 64 64 ms
AUTO REFRESH period tRFC 80 80
ns
5
Exit SELF REFRESH to ACTIVE command tXSR 80 80 5
Transition time tT 0.5 1.2 0.5 1.2
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IS42/45SM/RM/VM16800G
Note :
1. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to
reduce the data rate.
2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge
rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter.
3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid
data element will meet tOH before going High-Z.
5. Parameter guaranteed by design.
6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate
8. JEDEC and PC100 specify three clocks.
9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate.
10. A new command can be given tRC after self refresh exit.
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IS42/45SM/RM/VM16800G
Special Operation for Low Power Consumption
Temperature Compensated Self Refresh
Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to
the case temperature of the Mobile SDRAM device. This allows great power savings during SELF REFRESH during most operating
temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during
SELF REFRESH.
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on
temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed
more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature
range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to
accommodate the higher temperatures.
This temperature compensated refresh rate will save power when the DRAM is operating at normal temperatures.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be
refreshed during
SELF REFRESH. The refresh options are All Banks, Two Banks (bank a and b), One Bank (bank a), Half of One Bank
(1/2 of bank a), or Quarter of One Bank (1/4 of bank a). WRITE and READ commands can still occur during standard operation, but
only the selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled will be lost.
Deep Power Down
Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of
the devices. Data will not be retained once the device enters Deep Power Down Mode.
This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock,
while CKE is low. This mode is exited by asserting CKE high.

IS42RM16800G-75BLI-TR

Mfr. #:
Manufacturer:
Description:
DRAM 128M (8Mx16) 133MHz Mobile SDRAM, 2.5v
Lifecycle:
New from this manufacturer.
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