Table 6. Character Registers Format
Shutdown Mode (S Data Bit D0) Format
The S bit in the configuration register selects shutdown
or normal operation (Table 16). The display driver can
be programmed while in shutdown mode, and shut-
down mode is overridden when in display test mode.
For normal operation, set S bit to 1.
When the MAX6852 is in shutdown mode, the multiplex
oscillator is halted at the end of the current 100µs multi-
plex period (OSC = 4MHz), and the VFBLANK output is
used to disable the VFD tube driver. Data in the digit
and other control registers remains unaltered.
If the PUMP output is configured as a square-wave
clock, then the PUMP output is forced low for the dura-
tion of shutdown, and the square-wave clock restored
when the MAX6852 comes out of shutdown.
If the PHASE1 output or PHASE2 output is configured as
a filament driver, then that output is forced low for the
duration of shutdown and the filament drive waveforms
restored when the MAX6852 comes out of shutdown.
When the MAX6852 comes out of shutdown, the exter-
nal VFD tube driver is presumed to contain invalid data.
The VFBLANK output is used to disable the VFD tube
driver for the first multiplex cycle after exiting shutdown,
clearing any invalid data. The next multiplex cycle uses
newly sent valid data.
Configuration Lock (L Data Bit D1) Format
The configuration lock register is a safety feature to
reduce the risk of the VFD configuration settings being
inadvertently changed due to spurious writes if soft-
ware fails. When set, the shift-limit register (0x0E), grids
register (0x03), and output map data (0x06) can be
read but cannot be written. The output map data point-
er itself may be written in order to allow the output map
data to be read back (Table 17).
Blink Rate Selection (B Data Bit D2) Format
The B bit in the configuration register selects the blink
rate of the cursor and annunciator segments. This is the
speed that the segments blink on and off when blinking
is selected for these segments. The frequency of the
multiplex clock OSC and the setting of the B bit (Table
18) determine the blink rate.
Global Blink Timing Synchronization
(T Data Bit D4) Format
Setting the T bit in multiple MAX6852s at the same time
(or in quick succession) synchronizes the blink timing
across all the devices (Table 19). The display multiplex-
ing sequence is also reset, which can give rise to a
one-time display flicker when the register is written.
Global Clear Digit Data (R Data Bit D5) Format
When the R bit (Table 20) is set, the segment and
annunciator data are cleared.
Display Mode (M Data Bit D6) Format
The M bit (Table 21) selects the display modes (Table 1).
The display modes trade maximum allowable number of
digits (mode 96/2) against the availability of annunciator
segments (mode 48/1).
Blink Phase Readback (P Data Bit D7) Format
When the configuration register is read, the P bit
reflects the blink phase pin at that time (Table 22).
Microcontroller 4-Wire Serial Interface
The MAX6852 communicates through an SPI-compati-
ble 4-wire serial interface (Figure 6). The interface has
three inputs, clock (SCLK), chip select (CS), data in
(DIN), and output data out (DOUT). CS must be low to
clock data into or out of the device, and DIN must be
stable when sampled on the rising edge of SCLK.
DOUT is not a specific pin, but instead, any of the
PUMP, PORT0, or PORT1 outputs can be configured to
be DOUT. DOUT is stable on the rising edge of SCLK.
While the SPI protocol expects DOUT to be high
impedance when the MAX6852 is not being accessed,
DOUT on the MAX6852 is never high impedance. SCLK
and DIN can be used to transmit data to other peripher-
als. The MAX6852 ignores all activity on SCLK and DIN
except when CS is low.
