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MAX6852AEE+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
MAX6852
4-Wire Interfaced, 5
✕
7 Matrix Vacuum-
Fluorescent Display Controller
22 ______________________________________________________________________________________
REGISTER DATA
FONT
CHARACTER
FONT ADDRESS
POINTER
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
RAM00 0x00 0x05 0 0 1 1 1 1 1 0
RAM00 0x01 0x05 0 1 0 1 0001
RAM00 0x02 0x05 0 1 001 001
RAM00 0x03 0x05 0 1 0001 0 1
RAM00 0x04 0x05 0 0 1 1 1 1 1 0
RAM01 0x05 0x05 00000000
RAM01 0x06 0x05 0 1 00001 0
RAM01 0x07 0x05 0 1 1 1 1 1 1 1
RAM01 0x08 0x05 0 1 000000
RAM01 0x09 0x05 00000000
RAM02 0x0A 0x05 0 1 00001 0
RAM02 0x0B 0x05 0 1 1 00001
RAM02 0x0C 0x05 0 1 0 1 0001
RAM02 0x0D 0x05 0 1 001 001
RAM02 0x0E 0x05 0 1 0001 1 0
Table 11. User-Definable Character Storage Example
COMMAND
ADDRESS
REGISTER
DATA
ACTION BEING PERFORMED
0x05 0x8A Set font address pointer to the base address of font character RAM02.
0x05 0x42
1st 7 bits of data: 1000010 goes to font address 0x8A; pointer then autoincrements to address 0x8B.
0x05 0x61
2nd 7 bits of data: 1100001 goes to font address 0x8B; pointer then autoincrements to address 0x8C.
0x05 0x51
3rd 7 bits of data: 1010001 goes to font address 0x8C; pointer then autoincrements to address 0x8D.
0x05 0x49
4th 7 bits of data: 1001001 goes to font address 0x8D; pointer then autoincrements to address 0x8E.
0x05 0x46
5th 7 bits of data: 1000110 goes to font address 0x8E; pointer then autoincrements to address 0x8F.
Table 12. Setting a Font Character to RAM Example
REGISTER DATA
MODE
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1
D0
Cursor register. 0x0F
BLINK
CURSOR POSITION
Digit 1's cursor is lit continuously. 0x0F 0 0
0
000
0
0
Digit 1's cursor is lit only for the first half of each blink
period.
0x0F 1 0
0
000
0
0
UP TO 0x0F UP TO
Digit 96's cursor is lit continuously. 0x0F 0 1
0
111
1
1
Digit 96's cursor is lit only for the first half of each blink
period.
0x0F 1 1
0
111
1
1
No cursor is lit. 0x0F X 1
1XXXX
X
Table 13. Cursor Register Format
MAX6852
4-Wire Interfaced, 5
✕
7 Matrix Vacuum-
Fluorescent Display Controller
______________________________________________________________________________________ 23
REGISTER DATA
ANNUNCIATOR BYTE
D7 D6 D5 D4 D3 D2 D1 D0
BIT ALLOCATIONS
ANNUNCIATOR
A4
ANNUNCIATOR
A3
ANNUNCIATOR
A2
ANNUNCIATOR
A1
Annunciator A1 is off. XXXXXX00
Annunciator A1 is lit only for the first half of each blink
period.
XXXXXX01
Annunciator A1 is lit only for the second half of each blink
period.
XXXXXX10
Annunciator A1 is lit continuously. XXXXXX11
Annunciator A2 is off. XXXX00XX
Annunciator A2 is lit only for the first half of each blink
period.
XXXX01XX
Annunciator A2 is lit only for the second half of each blink
period.
XXXX10XX
Annunciator A2 is lit continuously. XXXX11XX
Annunciator A3 is off. X X 0 0 X X X X
Annunciator A3 is lit only for the first half of each blink
period.
XX01XXXX
Annunciator A3 is lit only for the second half of each blink
period.
XX10XXXX
Annunciator A3 is lit continuously. X X 1 1 X X X X
Annunciator A4 is off. 0 0 X X X X X X
Annunciator A4 is lit only for the first half of each blink
period.
01XXXXXX
Annunciator A4 is lit only for the second half of each blink
period.
10XXXXXX
Annunciator A4 is lit continuously. 1 1 X X X X X X
Table 14. Annunciator Registers Format
REGISTER DATA
MODE
D7 D6 D5 D4 D3 D2 D1
D0
Configuration
register
PMRT XBL
S
Table 15. Configuration Register Format
REGISTER DATA
MODE
D7 D6 D5 D4 D3 D2 D1
D0
Shutdown
PMRT XB L
0
Normal operation
PMRT XB L
1
Table 16. Shutdown Control
(S Data Bit D0) Format
REGISTER DATA
MODE
D7 D6 D5 D4 D3 D2 D1 D0
Unlocked
PMRT XB 0 S
Locked
PMRT XB 1 S
Table 17. Configuration Lock
(L Data Bit D1) Format
MAX6852
4-Wire Interfaced, 5
✕
7 Matrix Vacuum-
Fluorescent Display Controller
24 ______________________________________________________________________________________
REGISTER DATA
MODE
D7 D6 D5 D4 D3 D2 D1 D0
Slow blinking (cursor and annunciators blink on for 1s, off for 1s, for OSC = 4MHz)
PMRT X 0 L S
Fast blinking (cursor and annunciators blink on for 0.5s, off for 0.5s, for OSC = 4MHz)
PMRT X 1 L S
Table 18. Blink Rate Selection (B Data Bit D2) Format
REGISTER DATA
MODE
D7 D6 D5 D4 D3 D2 D1
D0
Blink timing counters are unaffected.
PMR0 XB L
S
Blink timing counters are cleared on the rising edge of CS.
PMR1 XB L
S
Table 19. Global Blink Timing Synchronization (T Data Bit D4) Format
REGISTER DATA
MODE
D7 D6 D5 D4 D3 D2 D1
D0
Segment and annunciator data are unaffected.
PM0 TXBL
S
Segment and annunciator data (address range 0x20 to 0x7F) are cleared on the rising
edge of CS.
PM1 TXBL
S
Table 20. Global Clear Digit Data (R Data Bit D5) Format
REGISTER DATA
MODE DISPLAY TYPE
D7 D6 D5 D4 D3 D2 D1 D0
48/1 Up to 48 digits, 1 digit per grid P 0 R T X B L S
96/2 Up to 96 digits, 2 digits per grid P 1 R T X B L S
Table 21. Display Mode (M Data Bit D6) Format
REGISTER DATA
MODE
D7 D6 D5 D4 D3 D2 D1 D0
P1 blink phase 0 M R T X B L S
P0 blink phase 1 M R T X B L S
Table 22. Blink Phase Readback (P Data Bit D7) Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
COMMAND ADDRESS
MSB
REGISTER DATA
LSB
Table 23. Serial-Data Format (16 Bits)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

MAX6852AEE+T

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Buy MAX6852AEE+T
Manufacturer:
Maxim Integrated
Description:
IC VFD CTRLR MATRIX 16QSOP
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