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MAX6852AEE+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
MAX6852
4-Wire Interfaced, 5
✕
7 Matrix Vacuum-
Fluorescent Display Controller
28 ______________________________________________________________________________________
OUTPUT MAP RAM
ADDRESS
OUTPUT MAP RAM CODE ON
POWER-UP (DECIMAL)
FUNCTION MAPPED BY OUTPUT MAP RAM CODE
0x00 to 0x27 0–39 Grids 0–39
0x28, 0x29, 0x2A, 0x2B, 0x2C
48, 49, 50, 51, 52
5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1
0x2D, 0x2E, 0x2F, 0x30, 0x31
53, 54, 55, 56, 57
5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2
0x32, 0x33, 0x34, 0x35, 0x36 58, 59, 60, 61, 62
5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3
0x37, 0x38, 0x39, 0x3A, 0x3B
63, 64, 65, 66, 67
5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4
0x3C, 0x3D, 0x3E, 0x3F, 0x40
68, 69, 70, 71, 72
5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5
0x41, 0x42, 0x43, 0x44, 0x45 73, 74, 75, 76, 77
5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6
0x46, 0x47, 0x48, 0x49, 0x4A 78, 79, 80, 81, 82
5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7
0x4B 83 5 x 7 matrix character segment DP
0x4C, 0x4D, 0x4E, 0x4F, 0x50
84, 85, 86, 87, 88
5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1
0x51, 0x52, 0x53, 0x54, 0x55 89, 90, 91, 92, 93
5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2
0x56, 0x57, 0x58, 0x59, 0x5A 94, 95, 96, 97, 98
5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3
0x5B, 0x5C, 0x5D, 0x5E, 0x5F
99, 100, 101,102, 103
5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4
0x60, 0x61, 0x62, 0x63, 0x64 104, 105, 106, 107, 108
5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5
0x65, 0x66, 0x67, 0x68, 0x69 109, 110, 111, 112, 113
5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6
0x6A, 0x6B, 0x6C, 0x6D, 0x6E
114, 115, 116, 117, 118
5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7
0x6F 119 5 x 7 matrix character segment DP
0x70 124 Cursor segment for digits 0 to 47 1st row
0x71 125 Cursor segment for digits 0 to 47 2nd row
0x72 to 0x79 127 No action
Table 30. Output Map RAM Initial Power-Up Status
REGISTER DATA
MODE
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1
D0
Set output map address to minimum (0x00) with data
0x80. (Note that this address is set as a power-up
default.)
0x06 1 0 0 0 0 0 0 0
Set output map address to maximum 0x79 with data
0xF9.
0x06 1 1 1 1 1 0 0 1
Table 31. Setting Output Map Address Pointer
REGISTER DATA
MODE
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1
D0
Write output map data; output map address pointer is
autoincremented after the output map data has been
written to the current location.
0x06 0 7 bits of output map data
Table 32. Writing Output Map Data
MAX6852
4-Wire Interfaced, 5
✕
7 Matrix Vacuum-
Fluorescent Display Controller
______________________________________________________________________________________ 29
REGISTER DATA
MODE
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1
D0
Read output map data; output map address pointer is
autoincremented after the output map data has been
read from the current location.
0x86 0 7 bits of output map data
Table 33. Reading Output Map Data
REGISTER DATA
FILAMENT DUTY CYCLE
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
HEX CODE
Minimum setting example (01) 0x09
00000001
0x01
Maximum setting example (199 or 0xC7) 0x09
11000111
0xC7
Table 35. Filament Duty-Cycle Register Format
REGISTER DATA
PHASE1 BEHAVIOR
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
HEX CODE
General-purpose output, logic 0.
This is the power-up condition.
0x0A
XXXXXX00
0xX0
General-purpose output, logic 1. 0x0A
XXXXXX01
0xX1
Output gives blink status:
0 if blink phase P0; 1 if blink phase P1.
0x0A
XXXXXX10
0xX2
Filament drive PHASE1 (logic 0 during
shutdown).
0x0A
XXXXXX11
0xX3
Table 36. PHASE1 Register Format
TIMING POINT
PHASE1 BEHAVIOR
PHASE2 BEHAVIOR
EXAMPLE 1
DUTY = 1 (MIN)
EXAMPLE 2
DUTY = 100
EXAMPLE 3
DUTY = 198
(A)
Low for (199 - FilOn)
cycles
Low for (199 - FilOn)
cycles
198 99 1
(B)
Low for (FilOn) cycles High for (FilOn) cycles
1 100 198
(C) Low for (2) cycles Low for (2) cycles 2 2 2
(D)
High for (FilOn) cycles Low for (FilOn) cycles
1 100 198
(E)
Low for (199 - FilOn)
cycles
Low for (199 - FilOn)
cycles
198 99 1
Total 4MHz
cycles
(OSC = 4MHz)
400 cycles = 100µs 400 cycles = 100µs
400 cycles =
100µs
400 cycles =
100µs
400 cycles =
100µs
Table 34. Filament Bridge Driver Timing
MAX6852
4-Wire Interfaced, 5
✕
7 Matrix Vacuum-
Fluorescent Display Controller
30 ______________________________________________________________________________________
REGISTER DATA
PHASE2 BEHAVIOR
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
HEX CODE
General-purpose output, logic 0.
This is the power-up condition.
0x0B
XXXXXX00
0xX0
General-purpose output, logic 1. 0x0B
XXXXXX01
0xX1
Output gives blink status: 0 if blink phase P0;
1 if blink phase P1.
0x0B
XXXXXX10
0xX2
Filament drive PHASE2 (logic 0 during
shutdown).
0x0B
XXXXXX11
0xX3
Table 37. PHASE2 Register Format
REGISTER DATA
PUMP PORT BEHAVIOR
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
HEX CODE
General-purpose output, logic 0.
This is the power-up condition.
0x08
XXXXXX
0 0 0xX0
General-purpose output, logic 1. 0x08
XXXXXX
0 1 0xX1
80kHz square-wave output (OSC = 4MHz)
(logic 0 during shutdown).
0x08
XXXXXX
1 0 0xX2
DOUT output. 0x08
XXXXXX
1 1 0xX3
Table 38. PUMP Register Format
REGISTER DATA
PORT0 PORT BEHAVIOR
COMMAND
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
HEX CODE
General-purpose output, logic 0.
This is the power-up condition.
0x0C
XXXXX
0 0 0 0xX0
General-purpose output, logic 1. 0x0C
XXXXX
0 0 1 0xX1
Outp ut g i ves b l i nk status: 0 i f b l i nk p hase P 0;
1 if blink phase P1.
0x0C
XXXXX
0 1 0 0xX2
DOUT output. 0x0C
XXXXX
0 1 1 0xX3
625Hz square-wave output zero in
shutdown.
0x0C
XXXXX
1 0 0 0xX4
1250Hz square-wave output zero in
shutdown.
0x0C
XXXXX
1 0 1 0xX5
2500Hz square-wave output zero in
shutdown.
0x0C
XXXXX
1 1 0 0xX6
Output gives shutdown status: 0 if
shutdown mode; 1 if operating mode.
0x0C
XXXXX
1 1 1 0xX7
Table 39. PORT0 Register Format
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

MAX6852AEE+T

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Buy MAX6852AEE+T
Manufacturer:
Maxim Integrated
Description:
IC VFD CTRLR MATRIX 16QSOP
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