MAX6852
4-Wire Interfaced, 5
✕
7 Matrix Vacuum-
Fluorescent Display Controller
20 ______________________________________________________________________________________
The multiplex clock frequency determines the multiplex
scan rate and the blink timing. The display scan rate is
{OSC / 400 / (1 + grids register value)}. There are 400
OSC cycles per digit multiplex period. For example,
with OSC = 4MHz, each display digit is enabled for
100µs. For a 40-grid display tube (grids register value
= 39 or 0x27), the display scan rate is 250Hz.
The BLINK output is the selectable blink period clock. It
is nominally 0.5Hz or 1Hz (OSC = 4MHz). It is low dur-
ing the first half of the blink period, and high during the
second half. The PORT0 and PORT1 general-purpose
outputs may be programmed to be BLINK output.
Synchronize the BLINK timing if desired by setting the
T bit in the configuration register (Table 19).
The RC oscillator uses an external resistor R
OSC
and
an external capacitor C
OSC
to set the oscillator fre-
quency. R
OSC
connects from OSC2 to ground. C
OSC
connects from OSC1 to ground. The recommended val-
ues of R
OSC
and C
OSC
set the oscillator to 4MHz,
which makes the BLINK frequencies 0.5Hz and 1 Hz:
f
OSC
= K
F
/ (R
OSC
x [C
OSC
+ C
STRAY
]) MHz
where:
K
F
= 2320
R
OSC
= external resistor in kΩ (allowable range 8kΩ to
80kΩ)
C
OSC
= external capacitor in pF
C
STRAY
= stray capacitance from OSC1 to GND in pF,
typically 2pF
For OSC = 4MHz, R
OSC
is 10kΩ and C
OSC
is 56pF.
The effective value of C
OSC
includes not only the actual
external capacitor used, but also the stray capacitance
from OSC1 to GND. This capacitance is usually in the
1pF-to-5pF range, depending on the layout used.
The allowed range of f
OSC
is 2MHz to 8MHz. If f
OSC
is
set too high, the internal oscillator can stop working. An
internal fail-safe circuit monitors the multiplex clock and
detects a slow or nonworking multiplex clock. When a
slow or nonworking multiplex clock is detected, an
internal fail-safe oscillator generates a replacement
clock of about 200kHz. This backup clock ensures that
the VFD is not damaged by the multiplex operation halt-
ing inadvertently. The scan rate for 16 digits is about
15Hz in fail-safe mode, and the display flickers. A flick-
ering display is a good indication that there is a prob-
lem with the multiplex clock.
Power Supplies
The MAX6852 operates from a single 2.7V to 3.6V
power supply. Bypass the power supply to GND with a
0.1µF capacitor as close to the device as possible. Add
a bulk capacitor (such as a low-cost electrolytic 1µF to
22µF) if the MAX6852 is driving high current from any of
the general-purpose output ports.
