MAX6852AEE+T Datasheet MAX6852AEE+, 4-103321-0-11, 4-103321-0-23 | P13-P15

MAX6852

4-Wire Interfaced, 5

7 Matrix Vacuum-

Fluorescent Display Controller

______________________________________________________________________________________ 13

Control and Operation Using the 4-Wire

Interface

Controlling the MAX6852 requires sending a 16-bit

word. The first byte, D15 through D8, is the command

address, and the second byte, D7 through D0, is the

data to be written to the command address (Table 23).

Connecting Multiple MAX6852s to the

4-Wire Bus

Daisy-chain multiple MAX6852s by connecting the

DOUT of one device to the DIN of the next, and driving

SCLK and CS lines in parallel. Data at DIN propagates

through the internal shift registers and appears at

DOUT 15.5 clock cycles later, clocked out on the rising

edge of SCLK. When sending commands to daisy-

chained MAX6852s, all devices are accessed at the

same time. An access requires (16 x n) clock cycles,

where n is the number of MAX6852s connected togeth-

er. To update just one device in a daisy-chain, send the

no-op command (0x00) to the others. Care must be

taken on power-up when daisy-chaining the serial inter-

face in this manner. Configure each MAX6852’s PORT0

or PORT1 outputs, in turn, to act as DOUT before data

propagates through it. For this reason, PORT0 is the

preferred output to configure as DOUT because its out-

put on power-up is low. This means that a daisy-

chained DIN input taking data from an uninitialized

PORT0 output clocks in 16 logic zeros, which is the

safe no-op instruction.

Writing Device Registers

The MAX6852 contains a 16-bit shift register into which

DIN is clocked on the rising edge of SCLK, when CS is

low. When CS is high, transitions on SCLK have no

effect. When CS goes high, the 16 bits in the shift regis-

ter are parallel loaded into a 16-bit latch. The 16 bits in

the latch are then decoded and executed.

The MAX6852 is written to using the following

sequence:

1) Take SCLK low.

2) Take CS low. This enables the internal 16-bit shift

3) Clock 16 bits of data into DIN, D15 first to D0 last,

observing the setup and hold times. Bit D15 is low,

indicating a write command.

4) Take CS high (while SCLK is still high after clocking

in the last data bit).

5) Take SCLK low.

Figure 7 shows a write operation when 16 bits are

transmitted.

RAM15

RAM14

RAM13

RAM12

RAM11

RAM10

RAM09

RAM08

RAM07

RAM05

RAM04

RAM03

RAM02

RAM01

RAM00

RAM16

RAM17

RAM18

RAM19

RAM20

RAM21

RAM23

1111

1110

1101

1100

1011

1010

1001

1000

0111

RAM06 RAM220110

0101

0100

0011

0010

0001

0000

MSB

LSB

x000

x001

x010

x011

x100

x101 x110 x111

Table 7. Character Map

MAX6852

4-Wire Interfaced, 5

7 Matrix Vacuum-

Fluorescent Display Controller

14 ______________________________________________________________________________________

CLK

DIN

D15

= 0

D14

D13

D12

D11 D10

D4 D3 D2

DOUT

D15 = 0

Figure 7. 16-Bit Write Transmission to the MAX6852

If fewer or greater than 16 bits are clocked into the

MAX6852 between taking CS low and taking CS high

again, the MAX6852 stores the last 16 bits received,

including the previous transmission(s). The general

case is when n bits (where n > 16) are transmitted to

the MAX6852. The last bits comprising bits {n-15} to {n}

are retained and are parallel loaded into the 16-bit latch

as bits D15 to D0, respectively (Figure 8).

Reading Device Registers

Any register data within the MAX6852 may be read by

sending a logic high to bit D15. The sequence is:

1) Take SCLK low.

2) Take CS low. This enables the internal 16-bit shift

3) Clock 16 bits of data into DIN, D15 first to D0 last,

observing the setup and hold times. Bit D15 is high,

indicating a read command, and bits D14 through

D8 contain the address of the register to read. Bits

D7 to D0 contain dummy data, which is discarded.

4) Take CS high. Positions D7 through D0 in the shift

addressed by bits D15 through D8.

5) Take SCLK low.

6) Issue another read or write command (which can be

no-op), and examine the bit stream at DOUT; the

first 8 bits contain the address of the register that

was read (Note: The MSB, which was transmitted as

a 1 for a read command, may read back either as a

1 or a zero). The second 8 bits are the contents of

the register addressed by bits D14 through D8 in

Step 3.

VFD Driver Serial Interface

The VFD driver interface on the MAX6852 is a serial

interface using three output pins, VFLOAD, VFCLK, and

VFDOUT (Figure 9) to drive industry-standard, shift-reg-

CSS

CSH

CSW

SCLK

DIN

DN-1 D1 D0

D15

CSU

DOUT

Figure 6. 4-Wire Serial Interface Timing Diagram

MAX6852

4-Wire Interfaced, 5

7 Matrix Vacuum-

Fluorescent Display Controller

______________________________________________________________________________________ 15

ister, high-voltage grid/anode VFD tube drivers (Figures

3 and 4). The speed of VFCLK is 2MHz when OSC is

4MHz. The maximum speed of VFCLK is 4MHz when

OSC is 8MHz. This interface is used to transfer display

data from the MAX6852 to the VFD tube driver. The ser-

ial interface bit stream output is programmable up to

122 bits, which are labeled DD0–DD121.

The functions of the three interface pins are as follows:

VFCLK is the serial clock output, which shifts data on

its falling edge from the MAX6852’s 122-bit output shift

VFDOUT is the serial data output. The data changes on

VFCLK’s falling edge, and is stable when it is sampled

by the display driver on the rising edge of VFCLK.

VFLOAD is the latch-load output. VFLOAD is high to

transfer data from the display tube driver’s shift register to

the display driver’s output latch (transparent mode), and

low to retain that data in the display driver’s output latch.

A fourth output pin, VFBLANK, provides gating control

of the tube driver. VFBLANK can be configured to be

either high or low using the VBLANK polarity register

(Table 26) to enable the VFD tube driver. In the default

condition, VFBLANK is high to disable the VFD tube dri-

ver, which is expected to force its driver outputs low to

blank the display without altering the contents of its out-

put latches. In the default condition, VFBLANK is low to

enable its VFD tube driver outputs to follow the state of

the VFD tube driver’s output latches. The VFBLANK

output is used for PWM intensity control and to disable

the VFD tube driver in shutdown.

Multiplex Architecture

The multiplex engine transmits grid and anode control

data to the external VFD driver using the VFCLK, VFD-

OUT, and VFLOAD. The number of data bits m trans-

mitted is set by the user in the shift-limit register (Table

28). Figure 10 is the VFD multiplex timing diagram.

The essential rules for multiplex action are as follows:

• The external VFD driver’s data latch contains the

data for the current grid being displayed.

• The VFBLANK input is controlled to provide the

PWM intensity control.

• The VFCLK and VFDOUT outputs are used to fill the

external VFD driver’s shift register with the multiplex

data for the next grid, during the multiplex timeslot

for the current grid.

• The VFLOAD output loads the new grid-anode data

pattern at the start of its multiplex cycle.

Grids Register

The grids register sets how many grids are multiplexed

from 1 to 48 (Table 24).

When the grids register is written, the external VFD tube

driver is presumed to contain invalid data. The

VFBLANK output is used to disable the VFD tube driver

for the first multiplex cycle after exiting shutdown, clear-

ing any invalid data. The next multiplex cycle uses

newly sent, valid data. If the grids register is written

with an out-of-range value of 0x30 to 0xFF, then the

value 0x2F is stored instead.

Intensity Register

Digital control of display brightness is provided by

pulse-width modulation of the tube blanking time, which

is controlled by the lower nibble of the intensity register

(Table 25). The modulator scales the VFBLANK output

in 15 steps from a minimum of 1/16 up to 15/16 of each

grid’s multiplex period (Figure 11). Figure 12 shows the

modulator behavior when the VFBLANK polarity regis-

ter is set to 0x00 (Table 26), so VFBLANK is high to dis-

able (blank) the display.

The minimum off-time period of a 1/16 multiplex period

(6.25µs with OSC = 4MHz) is always at the start of the

multiplex cycle. This allows time for slow display drivers

to turn off, and slow display phosphors time to decay

CLK

DIN

BIT

N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2

DOUT

N-15 = 0

N-15

= 0

N-14 N-13 N-12 N-11 N-10 N-1

N-31 N-30 N-29 N-28 N-27 N-26 N-25 N-24

N-23

N-22 N-21 N-20 N-19

N-18

N-17 N-16

Figure 8. Transmission of More than 16 Bits to the MAX6852

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

MAX6852AEE+T

Mfr. #:

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IC VFD CTRLR MATRIX 16QSOP

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MAX6852AEE+T

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