Data Sheet ADV7280
Rev. A | Page 9 of 28
CLOCK AND I
2
C TIMING SPECIFICATIONS
A
VDD
, D
VDD
, P
VDD
, and M
VDD
= 1.71 V to 1.89 V, D
VDDIO
= 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. M
VDD
applies to the ADV7280-M only.
Table 6.
Parameter Symbol Min Typ Max Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency 28.63636 MHz
Frequency Stability ±50 ppm
I
2
C PORT
SCLK Frequency 400 kHz
SCLK Minimum Pulse Width High t
1
0.6 µs
SCLK Minimum Pulse Width Low t
2
1.3 µs
Hold Time (Start Condition)
t
3
0.6
µs
Setup Time (Start Condition) t
4
0.6 µs
SDATA Setup Time t
5
100 ns
SCLK and SDATA Rise Times t
6
300 ns
SCLK and SDATA Fall Times t
7
300 ns
Setup Time (Stop Condition) t
8
0.6 µs
RESET INPUT
RESET Pulse Width
5 ms
SDATA
SCLK
t
3
t
5
t
3
t
4
t
8
t
6
t
7
t
2
t
1
11634-003
Figure 5. I
2
C Timing Diagram
ADV7280 Data Sheet
Rev. A | Page 10 of 28
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter Rating
A
VDD
to DGND 2.2 V
D
VDD
to DGND
2.2 V
P
VDD
to DGND 2.2 V
M
VDD
to DGND
1
2.2 V
D
VDDIO
to DGND 4 V
P
VDD
to D
VDD
−0.9 V to +0.9 V
M
VDD
to D
VDD
1
−0.9 V to +0.9 V
A
VDD
to D
VDD
−0.9 V to +0.9 V
Digital Inputs Voltage DGND 0.3 V to D
VDDIO
+ 0.3 V
Digital Outputs Voltage DGND 0.3 V to D
VDDIO
+ 0.3 V
Analog Inputs to Ground Ground − 0.3 V to A
VDD
+ 0.3 V
Maximum Junction Temperature
(T
J
max)
140°C
Storage Temperature Range −65°C to +150°C
Infrared Reflow Soldering
(20 sec)
260°C
1
M
VDD
applies to the ADV7280-M only.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
These devices are high performance integrated circuits with
an ESD rating of <2 kV, and they are ESD sensitive. Proper
precautions must be taken for handling and assembly.
THERMAL RESISTANCE
The thermal resistance values in Table 8 are specified for the
device soldered onto a 4-layer printed circuit board (PCB) with
a common ground plane and with the exposed pad of the device
connected to DGND. The values in Table 8 are maximum values.
Table 8. Thermal Resistance for the 32-Lead LFCSP
Thermal Characteristic Symbol Value Unit
Junction-to-Ambient Thermal
Resistance (Still Air)
θ
JA
32.5 °C/W
Junction-to-Case Thermal
Resistance
θ
JC
2.3 °C/W
REFLOW SOLDER
The ADV7280/ADV7280-M are Pb-free, environmentally
friendly products. They are manufactured using the most up-to-
date materials and processes. The coating on the leads of each
device is 100% pure Sn electroplate. The devices are suitable for
Pb-free applications and can withstand surface-mount soldering
at up to 255°C (±5°C).
In addition, the ADV7280/ADV7280-M are backward-
compatible with conventional SnPb soldering processes. This
means that the electroplated Sn coating can be soldered with
Sn/Pb solder pastes at conventional reflow temperatures of
220°C to 235°C.
ESD CAUTION
Data Sheet ADV7280
Rev. A | Page 11 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
24
INTRQ
23
A
IN
4
22
A
IN
3
21
A
VDD
20
VREFN
19
VREFP
18
A
IN
2
17
A
IN
1
1
2
3
4
5
6
7
8
DGND
D
VDDIO
D
VDD
DGND
P7
P6
P5
P4
9
10
11
12
13
14
15
16
P3
P2
P1
P0
D
VDD
XTALP
XTALN
P
VDD
32
31
30
29
28
27
26
25
LLC
PWRDWN
HS
VS/FIELD/SFL
SCLK
SDATA
ALSB
RESET
ADV7280
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
11634-006
Figure 6. Pin Configuration, ADV7280
Table 9. Pin Function Descriptions, ADV7280
Pin No. Mnemonic Type Description
1, 4
DGND
Ground
Ground for Digital Supply.
2 D
VDDIO
Power Digital I/O Power Supply (1.8 V or 3.3 V).
3, 13 D
VDD
Power Digital Power Supply (1.8 V).
5 to 12 P7 to P0 Output Video Pixel Output Ports.
14 XTALP Output
Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external
1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280. The crystal used
with the ADV7280 must be a fundamental crystal.
15 XTALN Input
Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7280 must
be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used
to clock the ADV7280, the output of the oscillator is fed into the XTALN pin.
16 P
VDD
Power PLL Power Supply (1.8 V).
17, 18,
22, 23
A
IN
1 to A
IN
4
Input
Analog Video Input Channels.
19 VREFP Output Internal Voltage Reference Output.
20 VREFN Output Internal Voltage Reference Output.
21 A
VDD
Power Analog Power Supply (1.8 V).
24
INTRQ
Output
Interrupt Request Output. An interrupt occurs when certain signals are detected on the
input video.
25
RESET
Input
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to
reset the ADV7280 circuitry.
26 ALSB Input
This pin selects the I
2
C write address for the ADV7280. When ALSB is set to Logic 0, the write
address is 0x40; when ALSB is set to Logic 1, the write address is 0x42.
27
SDATA
Input/output
I
2
C Port Serial Data Input/Output.
28 SCLK Input I
2
C Port Serial Clock Input. The maximum clock rate is 400 kHz.
29 VS/FIELD/SFL Output
Vertical Synchronization Output Signal/Field Synchronization Output Signal/Subcarrier
Frequency Lock. When configured for the SFL function, this pin provides a serial output
stream that can be used to lock the subcarrier frequency when the ADV7280 decoder is
connected to any Analog Devices, Inc., digital video encoder.
30
HS
Output
Horizontal Synchronization Output Signal.
31
PWRDWN
Input Power-Down Pin. A logic low on this pin places the ADV7280 in power-down mode.
32 LLC Output
Line-Locked Output Clock for Output Pixel Data. The clock output is nominally 27 MHz, but
it increases or decreases according to the video line length.
EPAD (EP) Exposed Pad. The exposed pad must be connected to DGND.

ADV7280WBCPZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD Video Decoder
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