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ADV7280WBCPZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
ADV7280 Data Sheet
Rev. A | Page 6 of 28
ANALOG SPECIFICATIONS
A
VDD
, D
VDD
, P
VDD
, and M
VDD
= 1.71 V to 1.89 V, D
VDDIO
= 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. M
VDD
applies to the ADV7280-M only.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 µF
Input Impedance Clamps switched off 10 MΩ
Large Clamp Source Current 0.4 mA
Large Clamp Sink Current
0.4
mA
Fine Clamp Source Current 10 µA
Fine Clamp Sink Current 10 µA
MIPI VIDEO OUTPUT SPECIFICATIONS (ADV7280-M ONLY)
A
VDD
, D
VDD
, P
VDD
, and M
VDD
= 1.71 V to 1.89 V, D
VDDIO
= 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
The CSI-2 clock lane of the ADV7280-M remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this
reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed
measurements were performed with the ADV7280-M operating in progressive mode and with a nominal 432 Mbps output data rate.
Specifications guaranteed by characterization.
Table 4.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
UNIT INTERVAL UI
Interlaced Output 4.63 ns
Progressive Output 2.31 ns
DATA LANE LP TX DC SPECIFICATIONS
1
Thevenin Output High Level V
OH
1.1 1.2 1.3 V
Thevenin Output Low Level V
OL
−50 0 +50 mV
DATA LANE LP TX AC SPECIFICATIONS
1
Rise Time, 15% to 85% 25 ns
Fall Time, 85% to 15% 25 ns
Rise Time, 30% to 85% 35 ns
Data Lane LP Slew Rate vs. C
LOAD
Maximum Slew Rate over Entire
Vertical Edge Region
Rising edge 150 mV/ns
Falling edge 150 mV/ns
Minimum Slew Rate
400 mV ≤ V
OUT
≤ 930 mV Falling edge 30 mV/ns
400 mV ≤ V
OUT
≤ 700 mV Rising edge 30 mV/ns
700 mV ≤ V
OUT
≤ 930 mV Rising edge >0 mV/ns
Pulse Width of LP Exclusive-OR Clock
First clock pulse after stop state
or last pulse before stop state
40 ns
All other clock pulses 20 ns
Period of LP Exclusive-OR Clock 90 ns
CLOCK LANE LP TX DC SPECIFICATIONS
1
Thevenin Output High Level V
OH
1.1 1.2 1.3 V
Thevenin Output Low Level V
OL
−50 0 +50 mV
CLOCK LANE LP TX AC SPECIFICATIONS
1
Rise Time, 15% to 85% 25 ns
Fall Time, 85% to 15% 25 ns
Data Sheet ADV7280
Rev. A | Page 7 of 28
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Clock Lane LP Slew Rate
Maximum Slew Rate over Entire
Vertical Edge Region
Rising edge 150 mV/ns
Falling edge 150 mV/ns
Minimum Slew Rate
400 mV ≤ V
OUT
≤ 930 mV Falling edge 30 mV/ns
400 mV ≤ V
OUT
≤ 700 mV Rising edge 30 mV/ns
700 mV ≤ V
OUT
≤ 930 mV Rising edge >0 mV/ns
DATA LANE HS TX SIGNALING
REQUIREMENTS
See Figure 3
Low Power to High Speed Transition
Stage
t
9
Time that the D0P pin is at V
OL
and the D0N pin is at V
OH
50 ns
t
10
Time that the D0P and D0N pins
are at V
OL
40 + (4 × UI) 85 + (6 × UI) ns
t
11
t
10
plus the HS-zero period 145 + (10 × UI) ns
High Speed Differential Voltage Swing |V
1
| 140 200 270 mV p-p
Differential Voltage Mismatch 10 mV
Single-Ended Output High Voltages
360 mV
Static Common-Mode Voltage Level
150
200
250
mV
Static Common-Mode Voltage
Mismatch
5 mV
Dynamic Common Level Variations
50 MHz to 450 MHz 25 mV
Above 450 MHz 15 mV
Rise Time, 20% to 80%
0.15
0.3 × UI
ns
Fall Time, 80% to 20% 0.15 0.3 × UI ns
High Speed to Low Power Transition
Stage
t
12
Time that the ADV7280-M drives
the flipped last data bit after
sending the last payload data bit
of an HS transmission burst
60 + (4 × UI) ns
t
13
Post-end-of-transmission rise
time (30% to 85%)
35 ns
t
14
Time from start of t
12
to start of
low power state following an HS
transmission burst
105 + (12 × UI) ns
t
15
Time that a low power state is
transmitted after an HS trans-
mission burst
100
ns
CLOCK LANE HS TX SIGNALING
REQUIREMENTS
See Figure 3
Low Power to High Speed Transition
Stage
2
t
9
Time that the CLKP pin is at V
OL
and the CLKN pin is at V
OH
50 ns
Time that the CLKP and CLKN
pins are at V
OL
38 95 ns
Clock HS-zero period 300 500 ns
High Speed Differential Voltage Swing |V
2
| 140 200 270 mV p-p
Differential Voltage Mismatch 10 mV
Single-Ended Output High Voltages 360 mV
Static Common-Mode Voltage Level 150 200 250 mV
Static Common-Mode Voltage
Mismatch
5
mV
Dynamic Common Level Variations
50 MHz to 450 MHz 25 mV
Above 450 MHz 15 mV
Rise Time, 20% to 80% 0.15 0.3 × UI ns
Fall Time, 80% to 20% 0.15 0.3 × UI ns
ADV7280 Data Sheet
Rev. A | Page 8 of 28
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
HS TX CLOCK TO DATA LANE TIMING
REQUIREMENTS
Data to Clock Skew 0.35 × UI 0.65 × UI ns
1
These measurements were performed with C
LOAD
= 50 pF.
2
The clock lane remains in high speed mode throughout normal operation. These results apply only to the ADV7280-M during startup.
11634-005
t
15
t
12
t
14
t
13
V
OH
V
OL
CLKP/CLKN
t
11
t
10
t
9
D0P/D0N
|V
2
|
|V
1
|
TRANSMIT FIRST
DATA BIT
LOW POWER
TO
HIGH SPEED
TRANSITION
START OF
TRANSMISSION
SEQUENCE
HIGH SPEED DATA
TRANSMISSION
HS-ZERO
HS-TRAIL HIGH SPEED
TO
LOW POWER
TRANSITION
Figure 3. ADV7280-M Output Timing Diagram (Conforms with MIPI CSI-2 Specification)
PIXEL PORT TIMING SPECIFICATIONS (ADV7280 ONLY)
A
VDD
, D
VDD
, and P
VDD
= 1.71 V to 1.89 V, D
VDDIO
= 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization.
Table 5.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
CLOCK OUTPUTS
LLC Mark Space Ratio t
9
:t
10
45:55 55:45 % duty cycle
DATA AND CONTROL OUTPUTS
Data Output Transitional Time t
11
Negative clock edge to start of valid data
(t
SETUP
= t
10
− t
11
)
3.8 ns
t
12
End of valid data to negative clock edge
(t
HOLD
= t
9
− t
12
)
6.9 ns
OUTPUT LLC
OUTPUTS P0 TO P7, HS,
VS/FIELD/SFL
t
9
t
10
t
11
t
12
11634-004
Figure 4. ADV7280 Pixel Port and Control Output Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

ADV7280WBCPZ-RL

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Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD Video Decoder
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