ADV7280 Data Sheet
Rev. A | Page 18 of 28
ADAPTIVE CONTRAST ENHANCEMENT (ACE)
The ADV7280/ADV7280-M can increase the contrast of an
image depending on the content of the picture, allowing bright
areas to be made brighter and dark areas to be made darker. The
optional ACE feature enables the contrast within dark areas to
be increased without significantly affecting the bright areas. The
ACE feature is particularly useful in automotive applications,
where it can be important to discern objects in shaded areas.
The ACE function is disabled by default. To enable the ACE
function, execute the register writes shown in Table 13. To
disable the ACE function, execute the register writes shown
in Table 14.
Table 13. Register Writes to Enable the ACE Function
Register Map
Register Address
Register Write
Description
User Sub Map (0x40 or 0x42) 0x0E 0x40 Enter User Sub Map 2
User Sub Map 2 (0x40 or 0x42)
0x80
0x80
Enable ACE
User Sub Map 2 (0x40 or 0x42) 0x0E 0x00 Reenter user sub map
Table 14. Register Writes to Disable the ACE Function
Register Map Register Address Register Write Description
User Sub Map (0x40 or 0x42) 0x0E 0x40 Enter User Sub Map 2
User Sub Map 2 (0x40 or 0x42) 0x80 0x00 Disable ACE
User Sub Map 2 (0x40 or 0x42) 0x0E 0x00 Reenter user sub map
Data Sheet ADV7280
Rev. A | Page 19 of 28
I2P FUNCTION
The advanced interlaced-to-progressive (I2P) function allows
the ADV7280/ADV7280-M to convert an interlaced video input
into a progressive video output. This function is performed with-
out the need for external memory. The ADV7280/ADV7280-M
use edge adaptive technology to minimize video defects on low
angle lines.
The I2P function is disabled by default. To enable the I2P
function, use the recommended scripts from Analog Devices.
ADV7280 Data Sheet
Rev. A | Page 20 of 28
MIPI CSI-2 OUTPUT (ADV7280-M ONLY)
The decoder in the ADV7280-M outputs an ITU-R BT.656 data
stream. The ITU-R BT.656 data stream is connected into a CSI-2
Tx module. Data from the CSI-2 Tx module is fed into a D-PHY
physical layer and output serially from the device.
The output of the ADV7280-M consists of a single data channel
on the D0P and D0N lanes and a clock channel on the CLKP and
CLKN lanes.
Video data is output over the data lanes in high speed mode. The
data lanes enter low power mode during the horizontal and vertical
blanking periods.
The clock lanes are used to clock the output video. After the
ADV7280-M is programmed, the clock lanes exit low power
mode and remain in high speed mode until the part is reset
or powered down.
The ADV7280-M outputs video data in an 8-bit YCrCb 4:2:2
format. When the I2P core is disabled, the video data is output in
an interlaced format at a nominal data rate of 216 Mbps. When
the I2P core is enabled, the video data is output in a progressive
format at a nominal data rate of 432 Mbps (see the I2P Function
section for more information).
D0P
(1 BIT)
D0N
(1 BIT)
CLKP
(1 BIT)
CLKN
(1 BIT)
ITU-R BT.656
DATA
STREAM
CSI-2
Tx
VIDEO
DECODER
D-PHY
Tx
ANALOG
VIDEO
INPUT
CSI Tx DATA
OUTPUT (8 BITS)
DATA LANE LP
SIGNALS (2 BITS)
CLOCK LANE LP
SIGNALS (2 BITS)
11634-011
Figure 10. MIPI CSI-2 Output Stage of the ADV7280-M

ADV7280WBCPZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD Video Decoder
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