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ADV7280WBCPZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
Data Sheet ADV7280
Rev. A | Page 15 of 28
POWER SUPPLY SEQUENCING
OPTIMAL POWER-UP SEQUENCE
The optimal power-up sequence for the ADV7280/ADV7280-M
is to first power up the 3.3 V D
VDDIO
supply, followed by the 1.8 V
supplies: D
VDD
, P
VDD
, A
VDD
, and M
VDD
(for the ADV7280-M).
When powering up the ADV7280/ADV7280-M, follow these steps.
During power-up, all supplies must adhere to the specifications
listed in the Absolute Maximum Ratings section.
1. Assert the
PWRDWN
and
RESET
pins (pull the pins low).
2. Power up the D
VDDIO
supply.
3. After D
VDDIO
is fully asserted, power up the 1.8 V supplies.
4. After the 1.8 V supplies are fully asserted, pull the
PWRDWN
pin high.
5. Wait 5 ms and then pull the
RESET
pin high.
6. After all power supplies and the
PWRDWN
and
RESET
pins are powered up and stable, wait an additional 5 ms
before initiating I
2
C communication with the ADV7280/
ADV7280-M.
SIMPLIFIED POWER-UP SEQUENCE
Alternatively, the ADV7280/ADV7280-M can be powered up
by asserting all supplies and the
PWRDWN
and
RESET
pins
simultaneously. After this operation, perform a software reset,
then wait 10 ms before initiating I
2
C communication with the
ADV7280/ADV7280-M.
While the supplies are being established, care must be taken to
ensure that a lower rated supply does not go above a higher rated
supply level. During power-up, all supplies must adhere to the
specifications listed in the Absolute Maximum Ratings section.
POWER-DOWN SEQUENCE
The ADV7280/ADV7280-M supplies can be deasserted
simultaneously as long as D
VDDIO
does not go below a lower
rated supply.
UNIVERSAL POWER SUPPLY (ADV7280 ONLY)
The ADV7280-M model requires a D
VDDIO
supply at a nominal
value of 3.3 V. The ADV7280 model, however, can operate with
a D
VDDIO
supply at a nominal value of 1.8 V. Therefore, it is possible
to power up all the supplies for the ADV7280 (D
VDD
, P
VDD
, A
VDD
,
and D
VDDIO
) to 1.8 V.
When D
VDDIO
is at a nominal value of 1.8 V, power up the
ADV7280 as follows:
1. Follow the power-up sequence described in the Optimal
Power-Up Sequence section, but power up the D
VDDIO
supply
to 1.8 V instead of 3.3 V. Also, power up the
PWRDWN
and
RESET
pins to 1.8 V instead of 3.3 V.
2. Set the drive strengths of the digital outputs of the ADV7280
to their maximum setting.
3. Connect any pull-up resistors connected to pins on the
ADV7280 (such as the SCLK and SDATA pins) to 1.8 V
instead of 3.3 V.
3.3V
1.8V
VOLTAGE
TIME3.3V SUPPLY
POWER-UP
1.8V SUPPLIES
POWER-UP
3.3V SUPPLY PWRDWN PIN
PWRDWN PIN
POWER-UP
RESET PIN
POWER-UP
RESET PIN
1.8V SUPPLIES
5ms
RESET
OPERATION
5ms
WAIT
11634-008
Figure 8. Optimal Power-Up Sequence
ADV7280 Data Sheet
Rev. A | Page 16 of 28
INPUT NETWORK
An input network (external resistor and capacitor circuit)
is required on the A
IN
x input pins of the decoder. Figure 9
shows the input network to use on each A
IN
x input pin of
the ADV7280/ADV7280-M when any of the following video
input formats is used:
• Single-ended CVBS
• YC (S-Video)
• YPrPb
51Ω
A
IN
1 OF ADV7280
INPUT
CONNECTOR
VIDEO INPUT
FROM SOURCE
24Ω
100nF
EXT
ESD
1
1634-009
Figure 9. Input Network
The 24 Ω and 51 Ω resistors supply the 75 Ω end termination
required for the analog video input. These resistors also create a
resistor divider with a gain of 0.68. The resistor divider attenuates
the amplitude of the input analog video and scales the input to
the ADC range of the ADV7280/ADV7280-M. This allows an
input range to the ADV7280/ADV7280-M of up to 1.47 V p-to-p.
Note that amplifiers within the ADC restore the amplitude of the
input signal so that signal-to-noise ratio (SNR) performance is
maintained.
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into the A
IN
x pin of the ADV7280/
ADV7280-M. The clamping circuitry within the ADV7280/
ADV7280-M restores the dc bias of the input signal to the optimal
level before it is fed into the ADC of the ADV7280/ADV7280-M.
Data Sheet ADV7280
Rev. A | Page 17 of 28
INPUT CONFIGURATION
The input format of the ADV7280/ADV7280-M is specified
using the INSEL[4:0] bits (see Table 12). These bits also configure
the SDP core to process CVBS, Y/C (S-Video), or component
(YPrPb) format. The INSEL[4:0] bits are located in the user sub
map of the register space at Address 0x00[4:0]. For more infor-
mation about the registers, see the Register Maps section.
The INSEL[4:0] bits specify predefined analog input routing
schemes, eliminating the need for manual mux programming
and allowing the user to route the various video signal types
to the decoder. For example, if the CVBS input is selected, the
remaining channels are powered down.
Table 12. Input Format Specified by the INSEL[4:0] Bits
INSEL[4:0] Bit Value Video Format
Analog Inputs
ADV7280 ADV7280-M
00000 CVBS CVBS input on A
IN
1 CVBS input on A
IN
1
00001 CVBS CVBS input on A
IN
2 CVBS input on A
IN
2
00010 CVBS CVBS input on A
IN
3 CVBS input on A
IN
3
00011 CVBS CVBS input on A
IN
4 CVBS input on A
IN
4
00100 CVBS Reserved CVBS input on A
IN
5
00101 CVBS Reserved CVBS input on A
IN
6
00110
CVBS
Reserved
CVBS input on A
IN
7
00111 CVBS Reserved CVBS input on A
IN
8
01000 Y/C (S-Video)
Y input on A
IN
1;
C input on A
IN
2
Y input on A
IN
1;
C input on A
IN
2
01001 Y/C (S-Video)
Y input on A
IN
3;
C input on A
IN
4
Y input on A
IN
3;
C input on A
IN
4
01010
Y/C (S-Video)
Reserved
Y input on A
IN
5;
C input on A
IN
6
01011 Y/C (S-Video) Reserved
Y input on A
IN
7;
C input on A
IN
8
01100 YPrPb
Y input on A
IN
1;
Pb input on A
IN
2;
Pr input on A
IN
3
Y input on A
IN
1;
Pb input on A
IN
2;
Pr input on A
IN
3
01101 YPrPb Reserved
Y input on A
IN
4;
Pb input on A
IN
5;
Pr input on A
IN
6
01110 to 11111 Reserved Reserved Reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

ADV7280WBCPZ-RL

Mfr. #:
Buy ADV7280WBCPZ-RL
Manufacturer:
Analog Devices Inc.
Description:
Video ICs 10-bit SD Video Decoder
Lifecycle:
New from this manufacturer.
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