AD7829-1
Rev. 0 | Page 10 of 20
CIRCUIT INFORMATION
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
V
IN
D7
D6
D5
D4
D3
D2
D1
D0
DECODE
LOGIC
14
15
13
1
OUTPUT
REGISTER
OUTPUT
DRIVERS
REFERENCE
06179-006
CIRCUIT DESCRIPTION
The AD7829-1 consists of a track-and-hold amplifier followed
by a half-flash analog-to-digital converter. These devices use a
half-flash conversion technique where one 4-bit flash ADC is
used to achieve an 8-bit result. The 4-bit flash ADC contains a
sampling capacitor followed by 15 comparators that compare
the unknown input to a reference ladder to achieve a 4-bit result.
This first flash, that is, coarse conversion, provides the four
MSBs. For a full 8-bit reading to be realized, a second flash,
that is, a fine conversion, must be performed to provide the four
LSBs. The 8-bit word is then placed on the data output bus.
Figure 4 and Figure 5 show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes
into hold mode and holds the analog input for 120 ns. This is
the acquisition phase as shown in
Figure 4, when Switch 2 is in
Position A. At the point when the track-and-hold returns to its
track mode, this signal is sampled by the sampling capacitor as
Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically, the
first flash is complete after 100 ns, that is, at 220 ns, while the
end of the second flash and, hence, the 8-bit conversion result,
is available at 330 ns (minimum). The maximum conversion
time is 420 ns. As shown in
Figure 5. ADC Conversion Phase
HOLD HOLD
120ns
CONVST
EOC
CS
RD
DB0 TO DB7
t
2
TRACK
TRACK
VALID
DATA
t
1
t
3
06179-007
Figure 6, the track-and-hold returns
to track mode after 120 ns and starts the next acquisition before
the end of the current conversion.
Figure 8 shows the ADC
transfer function.
TIMING AND
CONTROL
LOGIC
R1
HOLD
SAMPLING
CAPACITOR
A
B
SW2
R16
R15
R14
R13
T/H 1
V
IN
D7
D6
D5
D4
D3
D2
D1
D0
DECODE
LOGIC
14
15
13
1
OUTPUT
REGISTER
OUTPUT
DRIVERS
REFERENCE
06179-005
Figure 6. Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAM
Figure 7 shows a typical connection diagram for the AD7829-1.
The AGND and DGND are connected together at the device for
good noise suppression. The parallel interface is implemented
using an 8-bit data bus. The end of conversion signal (
EOC
) idles
high, the falling edge of
CONVST
initiates a conversion, and at
the end of conversion the falling edge of
EOC
is used to initiate
an interrupt service routine (ISR) on a microprocessor (see the
Parallel Interface section). V
REF IN/OUT
and V
MID
are connected to a
voltage source, such as the AD780, while V
DD
is connected to a
voltage source that can vary from 4.5 V to 5.5 V (see
Tabl e 5 in
the
Analog Input section). When V
DD
is first connected, the
AD7829-1 powers up in a low current mode, that is, power-down.
Ensure that the
CONVST
line is not floating when V
DD
is applied,
because this can put the AD7829-1 into an unknown state.
Figure 4. ADC Acquisition Phase
