AD7829-1
Rev. 0 | Page 5 of 20
TIMING CHARACTERISTICS
V
REF IN/OUT
= 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
1, 2
5 V ± 10% 3 V ± 10% Unit Description
t
1
420 420 ns max Conversion time
t
2
20 20 ns min
Minimum CONVST
pulse width
t
3
30 30 ns min
Minimum time between the rising edge of RD
and the next falling edge of convert start
t
4
110 110 ns max
EOC
pulse width
70 70 ns min
t
5
10 10 ns max
RD
rising edge to EOC pulse high
t
6
0 0 ns min
CS
to RD setup time
t
7
0 0 ns min
CS
to RD hold time
t
8
30 30 ns min
Minimum RD
pulse width
t
9
3
10 20 ns max
Data access time after RD
low
t
10
4
5 5 ns min
Bus relinquish time after RD
high
20 20 ns max
t
11
10 10 ns min
Address setup time before the falling edge of RD
t
12
15 15 ns min
Address hold time after the falling edge of RD
t
13
200 200 ns min Minimum time between new channel selection and convert start
t
POWER UP
25 25 μs typ
Power-up time from the rising edge of CONVST
using on-chip reference
t
POWER UP
1 1 μs max
Power-up time from the rising edge of CONVST
using external 2.5 V reference
1
Sample tested to ensure compliance.
2
See Figure 21, Figure 22, and Figure 23.
3
Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with V
DD
= 5 V ± 10%, and the time required for an
output to cross 0.4 V or 2.0 V with V
DD
= 3 V ± 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
10
, quoted in the timing characteristics is the true bus relinquish time
of the part and, as such, is independent of external bus loading capacitances.
TIMING DIAGRAM
200µA I
OL
200µA I
OH
2.1V
TO OUTPUT
PIN
C
L
50pF
06179-002
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
