AD7829BRWZ-1RL7 Datasheet AD7829BRUZ-1, AD7829BRWZ-1, AD7829BRWZ-1RL7 | P13-P15

AD7829-1

Rev. 0 | Page 12 of 20

REF

MID

2.5V

AD7829-1

2.5V

06179-012

= 5V

INPUT SIGNAL RANGE

FOR VARIOUS V

MID

= N/C (1.25V)

MID

= 2.5V

MID

= 3.75V

= 3V

INPUT SIGNAL RANGE

FOR VARIOUS V

MID

= N/C (1V)

MID

= 1.5V

MID

= 2V

6179-010

Figure 11. Accommodating Bipolar Signals Using External V

MID

REF

MID

EXTERNAL

2.5V

MID

06179-013

AD7829-1

Figure 9. Analog Input Span Variation with V

MID

can be used to remove offsets in a system by applying the

offset to the V

MID

pin, as shown in

Figure 12. Accommodating Bipolar Signals Using Internal V

MID

Figure 10; or it can be used

to accommodate bipolar signals by applying V

MID

to a level-shifting

circuit before V

, as shown in

NOTE: Although there is a V

REF

pin from which a voltage

reference of 2.5 V can be sourced, or to which an external

reference can be applied, this does not provide an option of

varying the value of the voltage reference. As stated in the

specifications for the AD7829-1, the input voltage range at this

pin is 2.5 V ± 2%.

Figure 11. When V

MID

is being

driven by an external source, the source can be directly tied to

the level-shifting circuitry (see

Figure 11); however, if the internal

MID

, that is, the default value, is being used as an output, it must

be buffered before applying it to the level-shifting circuitry, because

the V

MID

pin has an impedance of approximately 6 kΩ (see

Analog Input Structure

Figure 12).

Figure 13 shows an equivalent circuit of the analog input

structure of the AD7829-1. The two diodes, D1 and D2, provide

ESD protection for the analog inputs. Care must be taken to

ensure that the analog input signal never exceeds the supply

rails by more than 200 mV. This causes these diodes to become

forward biased and start conducting current into the substrate.

20 mA is the maximum current these diodes can conduct

without causing irreversible damage to the part. However, it is

worth noting that a small amount of current (1 mA) conducted

into the substrate due to an overvoltage on an unselected channel

can cause inaccurate conversions on a selected channel.

MID

AD7829-1

MID

6179-011

Figure 10. Removing Offsets Using V

MID

AD7829-1

Rev. 0 | Page 13 of 20

CONVST

DB0 TO DB7

A0 TO A2

EOC

VALID

DATA

ADDRESS CHANNEL y

TRACK CHx

HOLD CHx

TRACK CHy

HOLD CHy

120ns

06179-015

Capacitor C2 in Figure 13 is typically about 4 pF and can be

primarily attributed to pin capacitance. The resistor, R1, is a

lumped component made up of the on resistance of several

components, including that of the multiplexer and the track-

and-hold. This resistor is typically about 310 Ω. Capacitor C1

is the track-and-hold capacitor and has a capacitance of 0.5 pF.

Switch 1 is the track-and-hold switch, while Switch 2 is that of

the sampling capacitor, as shown in

Figure 4 and Figure 5.

4pF

310Ω

SW1

0.5pF

SW2

6179-014

Figure 14. Channel Hopping Timing

Figure 13. Equivalent Analog Input Circuit

There is a minimum time delay between the falling edge of

and the next falling edge of the

CONVST

signal, t

. This is the

minimum acquisition time required of the track-and-hold to

maintain 8-bit performance.

When in track phase, Switch 1 is closed and Switch 2 is in

Position A; when in hold mode, Switch 1 opens, while Switch 2

remains in Position A. The track-and-hold remains in hold

mode for 120 ns (see the

Figure 15 shows the typical

performance of the AD7829-1 when channel hopping for

various acquisition times. These results were obtained using an

external reference and internal V

MID

while channel hopping

between V

IN1

and V

IN4

with 0 V on Channel 4 and 0.5 V on

Channel 1.

Circuit Description section), after

which it returns to track mode and the ADC enters its

conversion phase. At this point, Switch 1 opens and Switch 2

moves to Position B. At the end of the conversion, Switch 2

moves back to Position A.

ACQUISITION TIME (ns)

8.0

5.0

10500 200

ENOB

100 50 40 30 20 15

7.5

7.0

6.5

6.0

5.5

8.5

06179-016

Analog Input Selection

On power-up, the default V

selection is V

IN1

. When returning

to normal operation from power-down, the V

selected is the

same one that was selected prior to power-down being initiated.

Tabl e 6 shows the multiplexer address corresponding to each

analog input from V

IN1

to V

IN8

for the AD7829-1.

Table 6.

A2 A1 A0 Analog Input Selected

0 0 0 V

IN1

0 0 1 V

IN2

0 1 0 V

IN3

0 1 1 V

IN4

1 0 0 V

IN5

Figure 15. Effective Number of Bits vs. Acquisition Time for the AD7829-1

1 0 1 V

IN6

1 1 0 V

IN7

The on-chip track-and-hold can accommodate input

frequencies to 10 MHz, making the AD7829-1 ideal for

subsampling applications. When the AD7829-1 is converting a

10 MHz input signal at a sampling rate of 2 MSPS, the effective

number of bits typically remains above seven, corresponding to

a signal-to-noise ratio of 42 dB, as shown in

1 1 1 V

IN8

Channel selection on the AD7829-1 is made without the

necessity of a write operation. The address of the next channel

to be converted is latched at the start of the current read

operation, that is, on the falling edge of

Figure 16.

RD CS

while is low, as

shown in

Figure 14. This allows for improved throughput rates

in “channel hopping” applications.

AD7829-1

Rev. 0 | Page 14 of 20

INPUT FREQUENCY (MHz)

010.2 1

SNR (dB)

34568

SAMPLE

= 2MHz

06179-017

CONVST

If the falling edge of

occurs after the required power-

up time has elapsed, then it is upon this falling edge that a

conversion is initiated. When using the on-chip reference, it is

necessary to wait the required power-up time of approximately

25 µs before initiating a conversion. That is, a falling edge on

CONVST

must not occur before the required power-up time

has elapsed, when V

is first connected or after the AD7829-1

has been powered down using the

CONVST

pin, as shown in

Figure 17.

POWER VS. THROUGHPUT

Superior power performance can be achieved by using the

automatic power-down (Mode 2) at the end of a conversion

(see the

Figure 16. SNR vs. Input Frequency on the AD7829-1

Operating Modes section).

POWER-UP TIMES

Figure 18 shows how the automatic power-down is implemented

using the

CONVST

signal to achieve the optimum power perform-

ance for the AD7829-1. The duration of the

The AD7829-1 has a 1 µs power-up time when using an

external reference and a 25 s power-up time when using the

on-chip reference. When V

is first connected, the AD7829-1

is in a low current mode of operation. Ensure that the

CONVST

pulse is

set to be equal to or less than the power-up time of the devices

(see the

CONVST

Operating Modes section). As the throughput rate is

reduced, the device remains in its power-down state longer, and the

average power consumption over time drops accordingly.

line is not floating when V

is applied. If there is a glitch on

CONVST

while V

is rising, the part attempts to power up

before V

has fully settled and may enter an unknown state.

In order to carry out a conversion, the AD7829-1 must first be

powered up.

POWER-UP

1µs

330ns

CONVERT

POWER-DOWN

CYCLE

10µs @ 100kSPS

CONVST

6179-019

POWER-UP

1µs

CONVST

POWER-UP

25µs

CONVERSION

INITIATED HERE

CONVERSION

INITIATED HERE

EXTERNAL REFERENCE

ON-CHIP REFERENCE

06179-018

Figure 18. Automatic Power-Down

For example, if the AD7829-1 is operated in a continuous

sampling mode, with a throughput rate of 100 kSPS and using

an external reference, the power consumption is calculated as

follows. The power dissipation during normal operation is

36 mW, V

= 3 V. If the power-up time is 1 s and the conversion

time is 330 ns (@ +25°C), the AD7829-1 can be said to dissipate

36 mW (maximum) for 1.33 µs during each conversion cycle.

If the throughput rate is 100 kSPS, the cycle time is 10 s and

the average power dissipated during each cycle is (1.33/10) ×

(36 mW) = 4.79 mW. This calculation uses the minimum

conversion time, thus giving the best-case power dissipation at

this throughput rate. However, the actual power dissipated

during each conversion cycle may increase, depending on the

actual conversion time (up to a maximum of 420 ns).

Figure 17. AD7829-1 Power-Up Time

CONVST

The AD7829-1 is powered up by a rising edge on the

pin. A conversion is initiated on the falling edge of

CONVST

Figure 17 shows how to power up the AD7829-1 when V

first connected or after the AD7829-1 has been powered down

using the

CONVST

pin when using either the on-chip reference

or an external reference. When using an external reference, the

falling edge of

CONVST

may occur before the required power-

up time has elapsed. However, the conversion is not initiated on

the falling edge of

CONVST

but rather at the moment when the

part has completely powered up, that is, after 1 µs.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

AD7829BRWZ-1RL7

Mfr. #:

Buy AD7829BRWZ-1RL7

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3V/5V 2MSPS 8-Bit 1-/4-/8-Ch Sampling

Lifecycle:

New from this manufacturer.

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AD7829BRWZ-1RL7

AD7829BRWZ-1RL7

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