MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
6 _______________________________________________________________________________________
Pin Description
PIN
QSOP TQFN
NAME FUNCTION
115V
LA
Port Supply for P1–P9. Connect V
LA
to a power supply between 1.62V and 5.5V.
Bypass V
LA
to GND with a 0.047µF ceramic capacitor.
2 16 AD0
Address Input. Sets the device slave address. Connect to GND, V
DD
, SCL, or SDA to
provide four address combinations.
31RST
Reset Inp ut. RST i s an acti ve- l ow i np ut, r efer enced to V
DD
, that cl ear s the 2- w i r e i nter face
and can b e confi g ur ed to p ut the d evi ce i n the p ow er - up r eset and /or to r eset the P W M
and b l i nk ti m i ng .
4 2 P1/INT
Input/Output Port. P1/INT is a general-purpose I/O that can be configured as a
transition detection interrupt output.
53
P2/OSCIN
Input/Output Port. P2/OSCIN is a general-purpose I/O that can be configured as the
oscillator input for PWM and blink features.
64
P3/OSCOUT
Input/Output Port. P3/OSCOUT is a general-purpose I/O that can be configured as the
PWM/blink/timing oscillator output for PWM and blink features.
7, 8, 9,
11, 12, 13
5, 6, 7,
9, 10, 11
P4–P9 Input/Output Ports. P4–P9 are general-purpose I/Os.
10 8 GND Ground
14 12 SCL Serial-Clock Input
15 13 SDA Serial-Data I/O
16 14 V
DD
Positive Supply Voltage. Bypass V
DD
to GND with a 0.047µF ceramic capacitor.
— EP EP Exposed Paddle on Package Underside. Connect to GND.
