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MAX7302ATE+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
_______________________________________________________________________________________ 7
Detailed Description
The MAX7302 9-port, general-purpose port expander
operates from a 1.62V to 3.6V power supply. Port P1
can be configured as an input and an open-drain out-
put. Port P1 can also be configured to function as an
INT output. Ports P2–P9 can be configured as inputs,
push-pull outputs, and open-drain outputs. Ports P2–P9
can be used as simple configurable logic arrays
(CLAs) to form user-defined logic gates.
Each port configured as an open-drain or push-pull
output can sink up to 25mA. Push-pull outputs also
have a 5mA source drive capability. The MAX7302 is
rated to sink a total of 100mA into any combination of
its output ports. Output ports have PWM and blink
capabilities, as well as logic drive.
Initial Power-Up
On power-up, the MAX7302 default configuration has all
9 ports, P1–P9, configured as input ports with logic lev-
els referenced to V
LA
. The transition detection interrupt
status flag resets and stays high (see Tables 1 and 2).
Device Configuration Registers
The device configuration registers set up the interrupt
function, serial-interface bus timeout, and PWM/blink
oscillator options, global blink period, and reset options
(see Tables 3 and 4).
I
2
C
OUTPUT
LOGIC
I/O
I/O
CONTROL
REGISTER
BANK
CLA
INPUT
LOGIC
P1–P9
V
LA
V
DD
SCL
AD0
GND
RST
SDA
MAX7302
Block Diagram
MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
8 _______________________________________________________________________________________
REGISTER ADDRESS
AUTOINCREMENT ADDRESS
POR STATE
Port P1 or INT Output 0x01 0x02 0x80
Port P2 or OSCIN Input 0x02 0x03 0x80
Port P3 or OSCOUT Output 0x03 0x04 0x80
Port P4 0x04 0x05 0x80
Port P5 0x05 0x06 0x80
Port P6 0x06 0x07 0x80
Port P7 0x07 0x08 0x80
Port P8 0x08 0x09 0x80
Port P9 0x09 0x0A or 0x4A 0x80
Configuration 26 0x26 0x27 0xCC
Configuration 27 0x27 0x28 0x8F
Ports P2–P5 Configurable Logic CLA0 0x28 0x29 0x00
Ports P6–P9 Configurable Logic CLA1 0x29 0x2A 0x00
Write Ports P2–P5 Same Data; Read P2 0x3C 0x3D 0x80
Write Ports P6–P9 Same Data; Read P6 0x3D 0x3E 0x80
FACTORY RESERVED (Do not write to these registers) 0x3C–0x3F 0x3F–0x40 0x00
CLA0 and CLA1 Configurable Logic Enable 0x70 0x71 0x00
CLA0 and CLA1 Configurable Logic Lock 0x71 0x72 0x00
Configuration 67 Lock, Ports P1–P5 Lock 0x72 0x73 0x00
Ports P6–P9 Lock 0x73 0x74 0xF0
FACTORY RESERVED (Do not write to these registers) 0x00 0x01 0x80
Table 1. Register Address Map
REGISTER DATA
REGISTER POWER-UP CONDITION
ADDRESS
CODE (HEX)
D7 D6 D5 D4 D3 D2 D1
D0
Ports P1–P9
Ports P_ are V
LA
-referred input ports with interrupt
and debounce disabled
0x01–0x09 1 0 0 0 0 0 0
0
Configuration 26
RS T d oes not r eset r eg i ster s or counters; b l i nk p er i od
i s 1H z; tr ansi ti on fl ag cl ear ; i nterr up t status fl ag cl ear
0x26
1100110
0
Configuration 27
Ports P1–P9 are GPIO ports; bus timeout is
disabled
0x27
1000111
1
Ports CLA0 to CLA1 Default gate structure
0x28–0x29 0 0 0 0 0 0 0
0
CLA0 to CLA1 CLA not enable 0x70
0000000
0
Configuration 27 Lock,
Ports P1–P5 Lock
Configuration 27 is not locked;
ports P1–P5 are not locked
0x72
0000000
0
Ports P6–P9 Lock Ports P6–P9 are not locked 0x73
1111000
0
Table 2. Power-Up Register Status
MAX7302
SMBus/I
2
C Interfaced 9-Port,
Level-Translating GPIO and LED Driver with CLA
_______________________________________________________________________________________ 9
REGISTER BIT DESCRIPTION
VALUE
FUNCTION
0 Enables the bus timeout feature.
D7 Bus timeout
1 Disables the bus timeout feature.
0 Reserved
D6, D5, D4 Reserved
1 Reserved
0 Sets P3 to output the oscillator.
D3 P3/OSCOUT
1* Sets P3 as a GPIO controlled by register 0x03.
0 Sets P2 as the oscillator input.
D2 P2/OSCIN
1* Sets P2 as a GPIO controlled by register 0x02.
0 Sets P1 as the interrupt output.
D1 P1/INT output
1 Sets P1 as a GPIO controlled by register 0x01.
D0 Input transition 0 Set to 0 on power-up to detect transition on inputs.
Table 4. Configuration Register (0x27)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
0 An interrupt has occurred on at least one interrupt enabled input port.
D7
Interrupt status flag
(read only)
1* No interrupt has occurred on an interrupt enabled input port.
0 A transition has occurred on an input port.
D6
Transition flag
(read only)
1* No transition has occurred on an input port.
D5 Reserved — Reserved
D4, D3, D2
Blink prescalor bits
0/1 Blink timer bits, see Table 10.
0* RST does not reset counters PWM/blink
D1 RST timer
1 RST resets PWM/blink counters
0* RST does not reset registers to power-on-reset state.
D0 RST POR
1 RST resets registers to power-on-reset state.
Table 3. Configuration Register (0x26)
*Default state.
*Default state.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

MAX7302ATE+T

Mfr. #:
Buy MAX7302ATE+T
Manufacturer:
Maxim Integrated
Description:
Interface - I/O Expanders 9-Port Level-Trans GPIO & LED Driver
Lifecycle:
New from this manufacturer.
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