© 2016 Integrated Device Technology, Inc.
Settling Time
64 ms
AD Conversion
768 ms
Calculation
160
m
s
DAC output
occurs here
DAC output
next update
Settling Time
64 ms
AD Conversion
768 ms
Calculation
160 ms
2.4. Output Stage
2.4.1. Digital to Analog Converter (Output DAC)
An 11-bit DAC, based on sub-ranging resistor strings, is used for the digital-to-analog output conversion in the
analog ratiometric and absolute analog voltage modes. Selection during calibration configures the system to
operate in either of these modes. The design allows for excellent testability as well as low power consumption.
Figure 2.2 shows the data timing of the DAC output with the 1 kHz update rate setting.
Figure 2.2 DAC Output Timing for Highest Update Rate
2.4.2. Output Buffer
A rail-to-rail operational amplifier (OpAmp) configured as a unity gain buffer can drive resistive loads (whether
pull-up or pull-down) as low as 2.5 kΩ and capacitances up to 15 nF. To limit the error due to amplifier offset
voltage, an error compensation circuit is included which tracks and reduces the offset voltage to < 1 mV.
2.4.3. Voltage Reference Block
A linear regulator control circuit is included in the Voltage Reference Block to interface with an external JFET
to allow operation in systems where the supply voltage exceeds 5.5 V. This circuit can also be used for over-
voltage protection. The regulator set point has a coarse adjustment via an EEPROM bit (see section 2.3.1), which
can adjust the set point around 5.0 V or 5.5 V. In addition, the 1 V trim setting (see below) can also act as a fine
adjustment for the regulation set point.
Note: If using the external JFET for over-voltage protection purposes (i.e., 5 V at JFET drain and expecting 5 V
at JFET source), there will be a voltage drop across the JFET; therefore ratiometricity will be compromised
somewhat depending on the rds(on) of the chosen JFET. A Vishay J107 is the best choice, because it has only
an 8 mV drop worst case. If using as regulation instead of over-voltage, an MMBF4392 also works well.
The Voltage Reference Block uses the absolute reference voltage provided by the Bandgap to produce two
regulated on-chip voltage references. A 1 V reference is used for the output DAC high reference, when the part is
configured for 0 to 1 V analog output. For this reason, the 1 V reference must be very accurate and includes trim,
such that its value can be trimmed within +/-3 mV of 1.0 V. The 1 V reference is also used as the on-chip
reference for the JFET regulator block, so the regulation set point of the JFET regulator can be fine-tuned, using
the 1 V trim. The 5 V reference can be trimmed within +/-15 mV. Table 2.1 shows the order of trim codes with
0111
B
for the lowest reference voltage, and 1000
B
for the highest reference voltage.
