ZSC31010CEG1-R Datasheet ZSC31010CEG1-R, ZSC31010CIG1-R, ZSC31010CIG1-T | P7-P9

ZSC31010 Datasheet

7

January 20, 2016

1.3. Electrical Parameters

See important table notes at the end of the table. Note: For parameters marked with an asterisk, there is no

verification in mass production; the parameter is guaranteed by design and/or quality observation.

Parameter Symbol Conditions Min Typ Max Unit

1.3.1. Supply/Regulation Characteristics

Supply Voltage V

DD

2.7 5.0 5.5 V

Supply Current (varies with

update rate and output mode)

I

DD

At minimum update rate 0.25

mA

At maximum update rate 1.0 1.2

Temperature Coefficient –

Regulator (worst case) *

TC

REG

Tem. -10°C to 120°C 35

ppm/K

Temp. < -10°C and > 120°C 100

Power Supply Rejection Ratio * PSRR DC < 100 Hz (JFET

regulation loop using

mmbf4392 and 0.1 µF

decoupling cap)

60 dB

AC < 100 kHz (JFET

regulation loop using

mmbf4392 and 0.1 mF

decoupling cap)

45 dB

Power-On Reset Level POR 1.4 2.6 V

1.3.2. Analog Front-End (AFE) Characteristics

Leakage Current Pin VBP,VBN I

IN_LEAK

±10

nA

1.3.3. EEPROM Parameters

Number Write Cycles n

WRI_EEP

At 150°C

At 85°C

100

100k

Cycles

Data Retention t

WRI_EEP

At 100°C

10 Years

1.3.4. A/D Converter Characteristics

ADC Resolution r

ADC

14 Bit

Integral Nonlinearity (INL)

1)

INL

ADC

-4 +4 LSB

Differential Nonlinearity (DNL) * DNL

ADC

-1 +1 LSB

Response Time T

RES,ADC

Varies with update rate.

Value given at fastest rate.

1 ms

1.3.5. Analog Output (DAC and Buffer) Characteristics

Max. Output Current I

OUT

Max. current maintaining

accuracy

2.2 mA

Resolution r

OUT

Referenced to V

DD

11 Bit

Absolute Error E

ABS

DAC input to output -10 +10 mV

Differential Nonlinearity * DNL No missing codes -0.9 +1.5 LSB

11Bit

Upper Output Voltage Limit V

OUT

R

L

= 2.5 kΩ

95% V

DD

Lower Output Voltage Limit V

OUT

16.5 mV

ZSC31010 Datasheet

8

January 20, 2016

Parameter Symbol Conditions Min Typ Max Unit

1.3.6. ZACwire™ Serial Interface

ZACwire

™

Line Resistance *

R

ZAC,line

The rise time T

ZAC,rise

must be

2 ∗ R

ZAC,line

∗ C

ZACload

≤ 5µs.

If using a pull-up resistor

instead of a line resistor, it

must meet this specification.

3.9

kΩ

ZACwire

™

Load Capacitance *

C

ZAC,load

0 1 15 nF

ZACwire

™

Rise Time *

T

ZAC,rise

5 µs

Voltage Level Low * V

ZAC,low

0 0.2 V

DD

Voltage Level High * V

ZAC,low

0.8 1 V

DD

1.3.7. System Response Characteristics

Start-Up-Time t

STA

Power-up to output 10 ms

Response Time t

RESP

Update_rate = 1 kHz (1 ms) 1 2 ms

Sampling Rate f

S

Update_rate = 1 kHz (1 ms) 1000 Hz

Overall Linearity Error

E

LIND

Bridge input to output –

Digital

0.025 0.04 %

Overall Linearity Error E

LINA

Bridge input to output –

Analog

0.1 0.2 %

Overall Ratiometricity Error

RE

out

±10%VDD, not using Bsink

feature

0.035 %

Overall Accuracy – Digital

(only IC, without sensor bridge)

AC

outD

-25°C to 85°C

±0.1%

%FSO

-50°C to 150°C

±0.25%

Overall Accuracy – Analog

(only IC, without sensor bridge)

2), 3)

AC

outA

-25°C to 85°C

±0.25%

%FSO

-40°C to 125°C

±0.35%

-50°C to 150°C

±0.5%

1)

Note: This is ± 4 LSBs to the 14-bit A-to-D conversion. This implies absolute accuracy to 12 bits on the A-to-D result.

Non-linearity is typically better at temperatures less than 125°C.

2)

Not included is the quantization noise of the DAC. The 11-bit DAC has a quantization noise of ± ½ LSB = 1.22 mV

(5V VDD) = 0.025%

3)

Analog output range 2.5% to 95%.

ZSC31010 Datasheet

9

January 20, 2016

1.4. Analog Inputs versus Output Resolution

The ZSC31010 incorporates an extended 14-bit charge-balanced ADC, which allows for a single gain setting on

the pre-amplifier to handle bridge sensitivities from 1.2 to 36 mV/V while maintaining 8 to 12 bits of output reso-

lution with a default analog gain of 24. Selectable gain settings allow accommodating bridges with different

sensitivities. The tables below illustrate the minimum resolution achievable for a variety of bridge sensitivities. The

yellow shadowed fields indicate that for these input spans with the selected analog gain setting, the quantization

noise is higher than 0.1% FSO.

Table 1.1 ADC Resolution Characteristics for an Analog Gain of 6

Analog Gain 6

Input Span [mV/V]

Allowed Offset

(+/- % of Span)

1)

Minimum Guaranteed

Resolution [Bits]

Min Typ Max

57.3 80.0 105.8 38% 13.3

50.6 70.0 92.6 53% 13.1

43.4 60.0 79.4 73% 12.9

36.1 50.0 66.1 101% 12.6

28.9 40.0 52.9 142% 12.3

21.7 30.0 39.7 212% 11.9

1)

In addition to Tco, Tcg

Table 1.2 ADC Resolution Characteristics for an Analog Gain of 12

Analog Gain 12

Input Span [mV/V]

Allowed Offset

(+/- % of Span)

1)

Minimum Guaranteed

Resolution [Bits]

Min Typ Max

43.3 60.0 79.3 3% 13.0

36.1 50.0 66.1 17% 12.7

25.3 35.0 46.3 53% 12.2

18.0 25.0 33.0 101% 11.7

14.5 20.0 26.45 142% 11.4

7.2 10.0 13.22 351% 10.4

3.6 5.0 6.6 767% 9.4

1)

In addition to Tco, Tcg

Note: Yellow shadowing indicates that for these input spans with the selected analog gain setting, the quantization noise is > 0.1% FSO.

ZSC31010CEG1-R

ZSC31010CEG1-R

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