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ZSC31010CEG1-R

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43
ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
34
January 20, 2016
3.7. Reading EEPROM Contents
The contents of the entire EEPROM memory can be read using the Read EEPROM command (00
H
). This
command causes the IC to output consecutive bytes on the ZACwire™. After each transmission, the EEPROM
contents are shifted by 8 bits. The bit order of these bytes is given in Table 3.12.
Table 3.12 EEPROM Read Order
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 1
Offset_B[7:0]
Byte 2
Gain_T[1:0] Offset_B[13:8]
Byte 3
Offset_T[1:0] Gain_T[7:2]
Byte 4
T
SETL
[1:0] Offset_T[7:2]
Byte 5
Tcg[1:0] T
SETL
[7:2]
Byte 6
Tco[1:0] Tcg[7:2]
Byte 7
Tc_cfg[1:0] Tco[7:2]
Byte 8
SOT[5:0] Tc_cfg[3:2]
Byte 9
Osc_Trim[1:0] SOT_cfg[3:0] * SOT[7:6]
Byte 10
Output_
Select[0]
A2D_Offset[1:0] 1V_Trim[3:0] ** Osc_Trim[2]
Byte 11
Gain_B[2:0] JFET_Cfg[1:0] Update_Rate[1:0]
Output_
Select[1]
Byte 12
Gain_B[10:3]
Byte 13
Offset_B[3:0] *** Gain_B[14:11]
Byte 14
A5
H
* SOT_cfg/Pamp_Gain
** 1V_Trim/JFET_Trim
*** Duplicates first 4 bits of Byte 1
ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
35
January 20, 2016
4 Application Circuit Examples
Note: The typical output analog load resistor R
L
= 10 kΩ (minimum 2.5 kΩ). This optional load resistor can be
configured as a pull-up or pull-down. If it is configured as a pull-down, it cannot be part of the module to be
calibrated because this would prevent proper operation of the ZACwire™. If a pull-down load is desired, it must be
added to the system after module calibration.
There is no output load capacitance needed.
EEPROM contents: OUTPUT_select, JFET_Cfg, 1V_Trim/JFET-Trim
4.1. Three-Wire Rail-to-Rail Ratiometric Output
This example shows an application circuit for rail-to-rail ratiometric voltage output configuration with temperature
compensation via internal PTAT. The same circuitry is applicable for a 0 to 1 V absolute analog output.
Figure 4.1 Rail-to-Rail Ratiometric Voltage Output
2
1
5
6
7
8
3
4
ZSC31010
Bsink
VBP
N/C
VBN
VSS
SIG
TM
VDD
Vgate
0.1 mF
V
supply
Ground
+2.7 to +5.5 V
OUT
Optional Bsink
10 nF
The optional bridge sink allows power savings switching off the bridge current. The output voltage can be one of
the following options:
• Rail-to-rail ratiometric analog output V
DD
(= V
supply
).
• 0 to 1 V absolute analog output. The absolute voltage output reference is trimmable 1 V (±3 mV) in the 1 V
output mode via a 4-bit EEPROM field (see section 2.4.3).
ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
36
January 20, 2016
4.2. Absolute Analog Voltage Output
The figure below shows an application circuit for an absolute voltage output configuration with temperature
compensation via internal temperature PTAT, and external JFET regulation for all industry standard applications.
The gate-source cutoff voltage (V
GS
) of the selected JFET must be ≤ -2 V.
Figure 4.2 Absolute Analog Voltage Output
2
1
5
6
7
8
3
4
ZSC31010
Bsink
VBP
N
/C
VBN
VSS
SIG
TM
VDD
Vgate
0
.1 m
F
V
supply
Ground
+5
.5
to +
30
V
OUT
Optional Bsink
S D
MMBF4392
10 n
F
The output signal range can be one of the following options:
• 0 to 1 V analog output. The absolute voltage output reference is trimmable: 1 V (± 3 mV) in the 1 V output
mode via a 4-bit EEPROM field (see section 2.4.3).
• Rail-to-rail analog output. The on-chip reference for the JFET regulator block is trimmable: 5 V (± 15 mV) in
the ratiometric output mode via a 4-bit EEPROM field (see section 2.4.3).
4.3. Three-Wire Ratiometric Output with Over-Voltage Protection
The figure below shows an application circuit for a ratiometric output configuration with temperature compensation
via an internal diode. In this application, the JFET is used for over-voltage protection. JFET_Cfg bits [14:13] in
EEPROM are configured to 5.5 V. There is an additional maximum error of 8 mV caused by the non-zero r
ON
of
the limiter JFET.
Figure 4.3 Ratiometric Output, Temperature Compensation via Internal Diode
2
1
5
6
7
8
3
4
ZSC31010
Bsink
VBP
N/C
VBN
VSS
SIG
TM
VDD
Vgate
0.1 mF
V
supply
Ground
+4.5 to +5.5 V
OUT
Optional Bsink
S D
J107 Vishay
10 nF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P43

ZSC31010CEG1-R

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Description:
Sensor Interface Sensor Signal Conditoner
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