ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
19
January 20, 2016
3.2. ZACwire™ Communication Interface
3.2.1. Properties and Parameters
Table 3.1 Pin Configuration and Latch-Up Conditions
No.
Parameter
Symbol
Min
Typ
Max
Unit
Comments
1 Pull-up resistor (on-chip) R
ZAC,pu
30 k On-chip pull-
up resistor switched on during
Digital Output Mode and during CM Mode
(first 6 ms after power up)
2 Pull-up resistor (external) R
ZAC,pu_ext
150 If the master communicates via a push-
pull
stage, no pull-up resistor is needed;
otherwise, a pull-up resistor with a value of
at least 150 must be connected.
3 ZACwire™ rise time T
ZAC,rise
5 µs Any user RC network included in Sig™
path must meet this rise time
4 ZACwire™ line resistance
1)
R
ZAC,line
3.9 k Also see section 1.3.6 in the specification
tables.
5 ZACwire™ load capacitance
1)
C
ZAC,load
0 1 15 nF Also see section 1.3.6 in the specification
tables.
6 Voltage low level V
ZAC,low
0 0.2 V
DD
Rail-to-rail CMOS driver
7 Voltage high level V
ZAC,high
0.8 1 V
DD
Rail-to-rail CMOS driver
1)
The rise time must be T
ZAC,rise
= 2 R
ZAC,line
C
ZACload
5 ms . If using a pull-up resistor instead of a line resistor, it must meet this
specification.
ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
20
January 20, 2016
Bit Window
106.8 µsec @ 9.4kHz baud
40µsec @ 25kHz baud
Start Bit
Logic 1
Logic 0
P5 4 3 2
1 0S
Command Byte Data Byte
S
P
2
Start Bit
Parity Bit of Command or Data Byte
Command Bit (example:
Bit 2)
7 6 P5 4 3 2 1 07
6
2
Data Bit (example: Bit
2)
19-bit Frame (WRITE)
3.2.2. Bit Encoding
Figure 3.2 Manchester Duty Cycle
Start bit = 50% duty cycle used to set up strobe time
Logic 1 = 75% duty cycle
Logic 0 = 25% duty cycle
Stop Time
The ZACWire™ bus will be held high for 32 μs (nominal)
between consecutive data packets regardless of baud rate.
3.2.3. Write Operation from Master to ZSC31010
The calibration master sends a 19-bit packet frame to the ZSC31010.
Figure 3.3 19-Bit Write Frame
The incoming serial signal will be sampled at a 512 kHz clock rate. This protocol is very tolerant to clock skew and
can easily tolerate baud rates in the 6 kHz to 48 kHz range.
ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
21
January 20, 2016
S
Data Byte
S
P
Start Bit
Parity Bit of Data Byte
Data Bit (Low)
P
1 0
0
1 0
11
0
1
Data Bit (High
)
1 DATA Byte Packet
(
10-bit byte A5
H
)
0
3.2.4. ZSC31010 Read Operations
The incoming frame will be checked for proper parity on both, command and data bytes, as well as for any edge
time-outs prior to a full frame being received.
Once a command/data pair is received, the ZSC31010 will perform that command. After the command has been
successfully executed by the IC, the IC will acknowledge success by a transmission of an A5
H
-byte back to the
master. If the master does not receive an A5
H
transmission within 130 ms of issuing the command, it must
assume the command was either improperly received or could not be executed.
Figure 3.4 Read Acknowledge
The ZSC31010 transmits 10-bit bytes (1 start bit, 8 data bits, 1 parity bit). During calibration and configuration,
transmissions are normally either A5
H
or data. A5
H
indicates successful completion of a command. There are two
different digital output modes configurable (digital output with temperature, and digital output with only bridge
data). During Normal Operation Mode, if the part is configured for digital output of the bridge reading, it first
transmits the high byte of bridge data, followed by the low byte. The bridge data is 14 bits in resolution, so the
upper two bits of the high byte are always zero-padded. There is a 32 μs stop time when the bus is held high
between bytes in a packet.
Figure 3.5 Digital Output (NOM) Bridge Readings
2 DATA Byte Packet
(Digital Bridge Output
)
P
7
6
5
4
3
2
1
0
Stop
S
P
0
0
5
4
3
2
1
0
S
Data Byte
Bridge High
Data Byte
Bridge Low
S
P
2
Stop
Start Bit
Parity Bit of Data Byte
Data Bit (example: Bit 2)
32 μs

ZSC31010CEG1-T

Mfr. #:
Manufacturer:
IDT
Description:
Sensor Interface Sensor Signal Conditoner
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