ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
37
January 20, 2016
4.4. Digital Output
For all three circuits, the output signal can also be digital. Depending on the output select bits, the bridge signal,
or the bridge signal and temperature signal are sent.
For the digital output, no load resistor, or load capacity are necessary. No pull-down resistor is allowed. If a line
resistor or pull-up resistor is used, the requirement for the rise time must be met ( 5 µs). The IC output includes a
pull-up resistor of about 30 k. The digital output can easily be read by firmware from a microcontroller, and IDT
can provide the customer with software in developing the interface.
4.5. Output Short Protection
The output of the ZSC31010 has no short protection. Therefore, a resistor RSP in series with the output must be
added in the application module. Refer to Table 4.1 to determine the value of RSP
.
To minimize additional error caused by this resistor for the analog output voltage, the load impedance must meet
the following requirement:
R
L
>> R
SP
Table 4.1 Resistor Values for Short Protection
Temperature Range (T
AMBMAX
) Resistor R
SP
Note
Up to 85°C 51
R
SP
= V
DD
/I
max
with I
max
= ([(170°C - T
AMBMAX
)/(163°C/W)] - V
DD
I
DD
)
/
VDD
Up to125°C 100
Up to 150°C 240
Tested at V
DD
=5V for 20 minutes for T
AMBMAX
.
ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
38
January 20, 2016
5 Default EEPROM Settings
If needed, the default setting for the ZSC31010 can be reprogrammed as described in section 3.
Table 5.1 Factory Settings for the ZSC31010 EEPROM
EEPROM Range Name
Default Values (Hex)
Until Week 9/2006
Default Values (Hex)
Since Week 10/2006
Default Values (Hex)
Since Week 48/2008
2:0 Osc_Trim 0xX 0xX 0xX
6:3 1V_Trim/JFET_Trim 0xX 0xX 0xX
8:7 A2D_Offset 0x0 0x3 0x3
10:9 Output_Select 0x3 0x2 0x2
12:11 Update_Rate 0x2 0x1 0x1
14:13 JFET_Cfg 0x1 0x2 0x2
29:15 Gain_B 0x800 0x0 0x3FFF
43:30 Offset_B 0x0 0x203 0x00FF
51:44 Gain_T 0x80 0x80 0x80
59:52 Offset_T 0x0 0x0 0x0
67:60 T
SETL
0x0 0x0 0x0
75:68 Tcg 0x0 0x0 0x0
83:76 Tco 0xE 0x0 0x0
87:84 Tc_cfg 0x0 0x0 0x0
95:88 SOT 0x0 0x0 0x0
99:96
{SOT_cfg, Pamp_Gain} 0x1 0x5 0x5
ZSC31010 Datasheet
© 2016 Integrated Device Technology, Inc.
39
January 20, 2016
1
2
3
4
8
7
6
5
Bsink
VBP
N/C
VBN
VSS
SIG
TM
VDD
Vgate
6 Pin Configuration and Package
The standard package of the ZSC31010 is an SOP-8 (3.81 mm / 150 mil body) with a lead-pitch 1.27 mm / 50 mil.
Table 6.1 Storage and Soldering Conditions for the SOP-8 Package
Parameter Symbol Conditions Min Typ
Max Unit
Maximum Storage Temperature T
max
_
storage
Less than 10hrs, before mounting 150 °C
Minimum Storage Temperature T
min
_
storage
Store in original packing only -50 °C
Maximum Dry-Bake Temperature T
drybake
Less than100 hrs total, before
mounting
125 °C
Soldering Peak Temperature T
peak
Less than 30s
(IPC/JEDEC-STD-020 Standard)
260 °C
Figure 6.1 ZSC31010 Pin-Out Diagram
Table 6.2 ZSC31010 Pin Configuration
Pin No. Name Description
1 Bsink Optional ground connection for bridge ground. Used for power savings.
2 VBP Positive bridge connection
3 N/C No connection
4 VBN Negative bridge connection
5 Vgate Gate control for external JFET regulation/over-voltage protection
6 VDD Supply voltage (2.7 - 5.5 V)
7 SIG™ ZACwire™ interface (analog out, digital out, calibration interface)
8 VSS Ground supply

ZSC31010CEG1-T

Mfr. #:
Manufacturer:
IDT
Description:
Sensor Interface Sensor Signal Conditoner
Lifecycle:
New from this manufacturer.
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