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8SLVP1204ANLGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
8SLVP1204 REVISION D 6/8/15 1 ©2015 Integrated Device Technology, Inc.
DATA SHEET
Low Phase Noise, 2:4, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP1204
General Description
The 8SLVP1204 is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVP1204 is
characterized to operate from a 3.3V or 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVP1204 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Four low skew, low additive jitter LVPECL output pairs
• Two selectable, differential clock input pairs
• Differential PCLKx pairs can accept the following differential input
levels: LVDS, LVPECL, CML
• Differential PCLKx pairs can also accept single-ended LVCMOS
levels. See Section, “Applications Information”, section, “Wiring
the Differential Input to Accept Single-Ended Levels” (Figures 1A
and 1B)
• Maximum input clock frequency: 2GHz
• LVCMOS interface levels for the control input, (input select)
• Output skew: 5ps (typical), at 3.63V
• Propagation delay: 200ps (typical), at 3.63V
• Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
12kHz - 20MHz: 40fs (maximum), at 3.63V
• Maximum device current consumption (I
EE
): 60mA (maximum),
at 3.63V
• Full 3.3V±5%, 3.3V±10% or 2.5V±5% supply
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
• Supports case temperature 105°C operations
Block Diagram Pin Assignment
f
REF
PCLK0
nPCLK0
PCLK1
nPCLK1
SEL
V
REF
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Voltage
Reference
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
Pulldown
V
CC
V
CC
0
1
5 6 7 8
16 15 14 13
1
2
3
4
12
11
10
9
V
EE
SEL
PCLK1
nPCLK1
nQ1
Q1
nQ0
Q0
VCC
PCLK0
nPCLK0
V
REF
Q3
nQ2
Q2
nQ3
8SLVP1204
16-Lead, 3mm x 3mm VFQFN Package
8SLVP1204 DATA SHEET
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
2 REVISION D 6/8/15
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. SEL Input Selection Function Table
NOTE: SEL is an asynchronous control.
Number Name Type Description
1V
EE
Power
Negative supply pin.
2 SEL Input Pulldown
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL interface
levels.
3 PCLK1 Input Pulldown
Non-inverting differential LVPECL clock/data input.
4 nPCLK1 Input
Pullup/
Pulldown
Inverting differential LVPECL clock/data input. V
CC
/2 default when left floating.
5V
CC
Power
Power supply pins.
6 PCLK0 Input Pulldown
Non-inverting differential LVPECL clock/data input.
7 nPCLK0 Input
Pullup/
Pulldown
Inverting differential LVPECL clock/data input. V
CC
/2 default when left floating.
8V
REF
Output
Bias voltage reference for the PCLK inputs.
9, 10 Q0, nQ0 Output
Differential output pair 0. LVPECL interface levels.
11, 12 Q1, nQ1 Output
Differential output pair 1. LVPECL interface levels.
13, 14 Q2, nQ2 Output
Differential output pair 2. LVPECL interface levels.
15, 16 Q3, nQ3 Output
Differential output pair 3. LVPECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2 pF
R
PULLDOWN
Input Pulldown Resistor 51 k
R
PULLUP
Input Pullup Resistor 51 k
Input
OperationSEL
0 (default) PCLK0, nPCLK0 is the selected differential clock input.
1 PCLK1, nPCLK1 is the selected differential clock input.
REVISION D 6/8/15 3 LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8SLVP1204 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
NOTE 1: According to JEDEC/JESD 22-A114/22-C101.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= 3.3V ±10%, V
EE
= 0V, T
A
= -40°C to 85°C
Table 4B. Power Supply DC Characteristics, V
CC
= 3.3V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Table 4C. Power Supply DC Characteristics, V
CC
= 2.5V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Item Rating
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
50mA
100mA
Input Sink/Source, I
REF
±2mA
Maximum Junction Temperature, T
J,MAX
125°C
Storage Temperature, T
STG
-65°C to 150°C
ESD - Human Body Model, NOTE 1 2000V
ESD - Charged Device Model, NOTE 1 1500V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Power Supply Voltage 2.97 3.3V 3.63 V
I
EE
Power Supply Current 53 60 mA
I
CC
Power Supply Current Q0 to Q3 terminated 50 to V
CC
– 2V 170 204 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Power Supply Voltage 3.135 3.3V 3.465 V
I
EE
Power Supply Current 53 60 mA
I
CC
Power Supply Current Q0 to Q3 terminated 50 to V
CC
– 2V 170 204 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Power Supply Voltage 2.375 2.5V 2.625 V
I
EE
Power Supply Current 49 55 mA
I
CC
Power Supply Current Q0 to Q3 terminated 50 to V
CC
– 2V 170 199 mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

8SLVP1204ANLGI8

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Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2:4 LVPECL Output Fanout Buffer
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