REVISION D 6/8/15 7 LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8SLVP1204 DATA SHEET
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
NOTE 2. Measured from the differential input crossing point to the differential output crosspoint.
NOTE 3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
point.
NOTE 4. This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross
point.
NOTE 6. Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
NOTE 7. For single-ended LVCMOS input applications, refer to the Applications section Wiring the Differential Input Levels to Accept Sin-
gle-ended Levels (Figures 1 and 2).
NOTE 8. V
IL
should not be less than -0.3V. V
IH
should not be higher than V
CC
.
NOTE 9. Common mode input voltage is defined as the crosspoint.
Table 5B. AC Electrical Characteristics, V
CC
= 3.3V ±10%, V
EE
= 0V, T
A
= -40°C to 85°C
1
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
REF
Input
Frequency
PCLK[0:1],
nPCLK[0:1]
2GHz
V/t
Input
Edge Rate
PCLK[0:1],
nPCLK[0:1]
1.5 V/ns
t
PD
Propagation Delay
2
NOTE 2. Measured from the differential input crossing point to the differential output crosspoint.
PCKx, nPCLKx to any Qx, nQx
for V
PP
= 0.1V or 0.3V
120 230 325 ps
tsk(o) Output Skew
3
4
NOTE 3. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
point.
NOTE 4. This parameter is defined in accordance with JEDEC Standard 65
630ps
tsk(i) Input Skew
4
655ps
tsk(p) Pulse Skew f
REF
= 100MHz 7 25 ps
tsk(pp) Part-to-Part Skew
4
5
NOTE 5. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cros-
spoint.
200 ps
t
R
/ t
F
Output Rise/ Fall Time 20% to 80% 35 200 ps
MUX
ISOLATION
Mux Isolation
6
f
REF
= 100MHz 77 dB
V
PP
Peak-to-Peak Input
Voltage
7
f
REF
< 1.5 GHz 0.1 1.5 V
f
REF
> 1.5 GHz 0.2 1.5 V
V
CMR
Common Mode Input
Voltage
7
8
9
1.0 V
CC
– 0.6 V
V
PP
= > 247mV 0.8 V
CC
– 0.6 V
V
O
(pp)
Output Voltage Swing,
Peak-to-Peak
V
CC
= 3.3V, f
REF
2GHz 0.45 0.75 1.0 V
V
CC
= 2.5V, f
REF
2GHz 0.40.651.0V
V
DIFF_OUT
Differential Output
Voltage Swing,
Peak-to-Peak
V
CC
= 3.3V, f
REF
2GHz 0.9 1.5 2.0 V
V
CC
= 2.5V, f
REF
2GHz 0.8 1.3 2.0 V
8SLVP1204 DATA SHEET
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8 REVISION D 6/8/15
NOTE 6. Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
NOTE 7. For single-ended LVCMOS input applications, refer to the Applications section Wiring the Differential Input Levels to Accept Sin-
gle-ended Levels (Figures 1 and 2).
NOTE 8. V
IL
should not be less than -0.3V. V
IH
should not be higher than V
CC
.
NOTE 9. Common mode input voltage is defined as the crosspoint.
REVISION D 6/8/15 9 LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8SLVP1204 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
Offset from Carrier Frequency (Hz)
SSB Phase Noise dBc/Hz

8SLVP1204ANLGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2:4 LVPECL Output Fanout Buffer
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New from this manufacturer.
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