8SLVP1204 DATA SHEET
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
12 REVISION D 6/8/15
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
The 8SLVP1204 inputs can be interfaced to LVPECL, LVDS, CML or
LVCMOS drivers. Figure 1A illustrates how to DC couple a single
LVCMOS input to the 8SLVP1204. The value of the series resistance
RS is calculated as the difference between the transmission line
impedance and the driver output impedance. This resistor should be
placed close to the LVCMOS driver. To avoid cross-coupling of
single-ended LVCMOS signals, apply the LVCMOS signals to no
more than one PCLK input.
A practical method to implement Vth is shown in Figure 1B below.
The reference voltage Vth = V1 = V
CC
/2, is generated by the bias
resistors R1 and R2. The bypass capacitor (C1) is used to help filter
noise on the DC bias. This bias circuit should be located as close to
the input pin as possible.
The ratio of R1 and R2 might need to be adjusted to position the V1
in the center of the input voltage swing. For example, if the input clock
swing is 2.5V and V
CC
= 3.3V, R1 and R2 value should be adjusted
to set V1 at 1.25V. The values below apply when both the
single-ended swing and V
CC
are at the same voltage.
Figure 1A. DC-Coupling a Single LVCMOS Input to the
8SLVP1204
When using single-ended signaling, the noise rejection benefits of
differential signaling are reduced. Even though the differential input
can handle full rail LVCMOS signaling, it is recommended that the
amplitude be reduced, particularly if both input references are
LVCMOS to minimize cross talk. The datasheet specifies a lower
differential amplitude, however this only applies to differential signals.
For single-ended applications, the swing can be larger, however V
IL
cannot be less than -0.3V and V
IH
cannot be more than V
CC
+ 0.3V.
Figure 1B shows a way to attenuate the PCLK input level by a factor
of two as well as matching the transmission line between the
LVCMOS driver and the 8SLVP1204 at both the source and the load.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. R3 and R4 in parallel should equal the transmission
line impedance; for most 50 applications, R3 and R4 will be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver.
Though some of the recommended components of Figure 1B might
not be used, the pads should be placed in the layout so that they can
be utilized for debugging purposes. The datasheet specifications are
characterized and guaranteed by using a differential signal.
Figure 1B. Alternative DC Coupling a Single LVCMOS Input to the 8SLVP1204
RS
LVCMOS
V
th
=
V
IH
+ V
IL
2
V
th
V
IH
V
IL
Receiv er
+
-R4
100
R3
100
RS Zo = 50 Ohm
Ro
Driver
VCC
VCC
R2
1K
R1
1K
C1
0.1uF
Ro + Rs = Zo
V1
VC C VC C
