8SLVP1204 DATA SHEET
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
16 REVISION D 6/8/15
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are a low impedance follower output that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
REVISION D 6/8/15 17 LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
8SLVP1204 DATA SHEET
Termination for 2.5V LVPECL Outputs
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to V
CC
– 2V. For V
CC
= 2.5V, the V
CC
– 2V is very close to ground
level. The R3 in Figure 6B can be eliminated and the termination is
shown in Figure 6C.
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6C. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
2.5V
50
Ω
50
Ω
R1
250
Ω
R3
250
Ω
R2
62.5
Ω
R4
62.5
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50
Ω
50
Ω
R1
50
Ω
R2
50
Ω
+
2.5V LVPECL Driver
V
CC
= 2.5V
2.5V
50Ω
50Ω
R1
50
Ω
R2
50
Ω
R3
18
Ω
+
8SLVP1204 DATA SHEET
LOW PHASE NOISE, 2:4, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
18 REVISION D 6/8/15
3.3V ±10% Power Considerations
This section provides information on power dissipation and junction temperature for the 8SLVP1204.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8SLVP1204 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for V
CC
= 3.63V.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
The maximum current at 85° is as follows:
I
EE_MAX
= 65mA
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.63V * 60mA = 217.80mW
Power (outputs)
MAX
= 33.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 33.2mW = 132.8mW
Total Power_
MAX
(3.63V, with all outputs switching) = 217.80mW + 132.8mW = 350.60mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.351W * 74.7°C/W = 111.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance
JA
for 16-Lead VFQFN, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 74.7°C/W 65.3°C/W 58.5°C/W

8SLVP1204ANLGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 2:4 LVPECL Output Fanout Buffer
Lifecycle:
New from this manufacturer.
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