21
LTC2404/LTC2408
APPLICATIONS INFORMATION
WUU
U
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
While operating in the internal serial clock mode, the SCK
output of the ADC may be used as the multiplexer clock
(CLK). D
IN
is latched into the multiplexer on the rising
edge of CLK. As shown in Figure 10, the multiplexer
channel is selected by serial shifting a 4-bit word into the
D
IN
pin on the rising edge of CLK. The first bit is an enable
bit which must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the rising edge of CSADC (falling edge of
CSMUX), the new channel is selected and will be valid for
the next conversion. If D
IN
is held LOW during the data
output state, the previous channel selection remains valid.
Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first and 32nd
rising edge of SCK, see Figure 11. On the rising edge of
CSADC, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 32 bits of output data, aborting
an invalid conversion cycle, or synchronizing the start of
a conversion. If CSADC is pulled HIGH while the con-
verter is driving SCK LOW, the internal pull-up is not
available to restore SCK to a logic HIGH state. This will
cause the device to exit the internal serial clock mode on
the next falling edge of CSADC. This can be avoided by
adding an external 10k pull-up resistor to the SCK pin or
by never pulling CSADC HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2404/LTC2408’s internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
SCKCLK
SDO
D
IN
CSADC
CSMUX
t
EOCtest
MSB
EXRSIG
BIT8BIT12 BIT11 BIT10 BIT9BIT27 BIT26BIT28BIT29BIT30BIT31
24048 F11
TEST EOC
DON’T CARE DON’T CAREEN D2 D1 D0
Hi-Z Hi-ZHi-Z
TEST EOC TEST EOC
V
CC
CS
10k
F
O
V
REF
CSMUX
CSADC
SCK
CLK
MUXOUT
ADCIN
D
IN
GND SDO
0.1V
TO V
CC
CH0
TO CH7
–0.12V
REF
TO 1.12V
REF
2.7V TO 5.5V
LTC2404/LTC2408
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
Figure 11. Internal Serial Clock with Reduced Data Output Length Timing Diagram
