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LTC2404IG#TRPBF

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31
LTC2404/LTC2408
APPLICATIONS INFORMATION
WUU
U
68HC11
2404/08 F29
MISO (PD2)
9
TO
17
GND
1, 5, 6, 16, 18, 22, 27, 28
23
20
25
19
21
24
CSADC
CSMUX
SCK
CLK
D
IN
SDO
26
F
O
LTC2408
CH0 TO
CH7
MUXOUT
7 4 3 2, 8
10µF
5V
V
REF
ADCIN V
CC
V
CC
24-BIT
∆Σ ADC
SCK (PD4)
SS (PD5)
MOSI (PD3)
LTC1391
S0
S1
S2
S3
S4
S5
S6
S7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
1
2
3
4
5
6
7
8
D
CLK
CS
D
OUT
D
IN
15
10
11
13
12
Figure 29. Combining the LTC2408 with the LTC1391 for 16 Input Channels
Figure 28. LTC2408-68HC11 MCU Digital Interface Routine
*
***************************************
* The SPI data transfer *
***************************************
*
TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer
STAA SPDR This writes the byte into the SPI data register and
* starts the transfer
WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial
* transfer/exchange by reading the SPI Status Register
BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s
* MSB and is set to one at the end of an SPI transfer. The
* branch will occur while SPIF is a zero.
LDAA SPDR Load accumulator A with the current byte of LTC2408 data
* that was just received
STAA 0,X Transfer the LTC2408’s data to memory
INX Increment the pointer
CPX #DIN4+1 Has the last byte been transferred/exchanged?
BNE TRFLP1 If the last byte has not been reached, then proceed to
* the next byte for transfer/exchage
BSET PORTD,Y %00100000 This sets the SS* output bit to a logic
* high, de-selecting the LTC2408
PULA Restore the A register
PULY Restore the Y register
PULX Restore the X register
RTS
32
LTC2404/LTC2408
*****************************************************************************
* *
* This example program loads multiplexer channels selection data into *
* either the LTC2408’s internal MUX or an external LTC1391 MUX. It then *
* transfers the LTC2408’s 32-bit output conversion result to four *
* consecutive 8-bit memory locations. *
*
*
*****************************************************************************
*
***************************************
* 68HC11 register definitions *
***************************************
*
PORTD EQU $1008 Port D data register
* “ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
DDRD EQU $1009 Port D data direction register
SPCR EQU $1028 SPI control register
* “SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPSR EQU $1029 SPI status register
* “SPIF,WCOL, - ,MODF; - , - , - , - “
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
*
* RAM variables to hold the LTC2408’s 32 conversion result
*
DIN1 EQU $00 This memory location holds the LTC2408’s bits 31 - 24
DIN2 EQU $01 This memory location holds the LTC2408’s bits 23 - 16
DIN3 EQU $02 This memory location holds the LTC2408’s bits 15 - 08
DIN4 EQU $03 This memory location holds the LTC2408’s bits 07 - 00
MUX EQU $04 This memory location holds the MUX address data
*
***************************************
* Start GETDATA Routine *
***************************************
*
ORG $C000 Program start location
INIT1 LDAA #$2F -,-,1,0;1,1,1,1
* -, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set
LDAA #$38 -,-,1,1;1,0,0,0
STAA DDRD SS* , SCK, MOSI are configured as Outputs
* MISO, TxD, RxD are configured as Inputs
* DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA #$50
STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0
* and the clock rate is E/2
* (This assumes an E-Clock frequency of 4MHz. For higher
* E-Clock frequencies, change the above value of $50 to a
* value that ensures the SCK frequency is 2MHz or less.)
GETDATA PSHX
PSHY
PSHA
LDX #$0 The X register is used as a pointer to the memory
* locations that hold the conversion data
LDY #$1000
*
***************************************
* The next routine sends data to the *
* LTC2408 an sets its MUX channel *
***************************************
*
LDAA MUX Retrieve MUX address
TAB Save contents of Accum. A
SUBA #$07 Is the MUX address in the low nibble
BLE ENLWMX If it is, branch to enable the LTC2408’s internal MUX
TBA Restore contents of Accum. A
ORAA #$80 Enable the LTC1391 external MUX
BRA MUXSPI Go to SPI transfer2400
APPLICATIONS INFORMATION
WUU
U
33
LTC2404/LTC2408
APPLICATIONS INFORMATION
WUU
U
Figure 30. LTC2408/LTC1391-684C11 MCU Digital Interface Routine
ENLWMX TBA Restore contents of Accum. A
ORAA #$08 Set the MUX’s ENABLE bit
MUXSPI STAA SPDR Transfer Accum. A contents to SPI register to initiate
* serial transfer
WAITMUX LDAA SPSR Get SPI transfer status
BPL WAITMUX If the transfer is not finished, read status
*
***************************************
* Enable the LTC2408 *
***************************************
*
BCLR PORTD,Y %00100000 This sets the SS* output bit to a logic
* low, selecting the LTC2408
*
***************************************
* The next short loop waits for the *
* LTC2408’s conversion to finish before *
* starting the SPI data transfer *
***************************************
*
CONVEND LDAA PORTD Retrieve the contents of port D
ANDA #%00000100 Look at bit 2
* Bit 2 = Hi; the LTC2408’s conversion is not
* complete
* Bit 2 = Lo; the LTC2408’s conversion is complete
BNE CONVEND Branch to the loop’s beginning while bit 2 remains
* high
*
***************************************
* The SPI data transfer *
***************************************
*
TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer
STAA SPDR This writes the byte into the SPI data register and
* starts the transfer
WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial
* transfer/exchange by reading the SPI Status Register
BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s
* MSB and is set to one at the end of an SPI transfer. The
* branch will occur while SPIF is a zero.
LDAA SPDR Load accumulator A with the current byte of LTC2408 data
* that was just received
STAA 0,X Transfer the LTC2408’s data to memory
INX Increment the pointer
CPX #DIN4+1 Has the last byte been transferred/exchanged?
BNE TRFLP1 If the last byte has not been reached, then proceed to
* the next byte for transfer/exchage
BSET PORTD,Y %00100000 This sets the SS* output bit to a logic
* high, de-selecting the LTC2408
PULA Restore the A register
PULY Restore the Y register
PULX Restore the X register
RTS
An 8-Channel DC-to-Daylight Digitizer
The circuit in Figure 31 shows an example of the LTC2408’s
flexibility in digitizing a number of real-world physical
phenomena—from DC voltages to ultraviolet light. All of
the examples implement single-ended signal condition-
ing. Although differential signal conditioning is a preferred
approach in applications where the sensor is a bridge-
type, is located some distance from the ADC or operates
in a high ambient noise environment, the LTC2408’s low
power dissipation allows circuit operation in close prox-
imity to the sensor. As a result, conditioning the sensor
output can be greatly simplified through the use of single-
ended arrangements. In those applications where differ-
ential signal conditioning is required, chopper
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LTC2404IG#TRPBF

Mfr. #:
Buy LTC2404IG#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 24-Bit Power 4/Ch Delta-Sigma ADC
Lifecycle:
New from this manufacturer.
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