28
LTC2404/LTC2408
APPLICATIONS INFORMATION
WUU
U
2404/08 F25
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
9
10
11
12
13
14
15
17
8-CHANNEL
MUX
GND
1, 5, 6, 16, 18, 22, 27, 28
23
20
25
19
21
24
CSADC
CSMUX
SCK
CLK
D
IN
SDO
26
F
O
LTC2408
ADCINMUXOUT
74
6
2
4
8
16
32
64
128
AV = 1, 2, 4...1283
V
IN
2
5V
10k
10k20k
10k20k
10k20k
10k20k
10k20k
10k20k
10k20k
3 2, 8
1µF
5V
V
REF
V
CC
V
CC
+
LTC1050
0.1V TO V
CC
24-BIT
Σ ADC
Figure 25. Using the Multiplexer to Produce Programmable Gains of 1 to 128
2404/08 F26
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
9
10
11
12
13
14
15
17
8-CHANNEL
MUX
ANALOG
INPUTS
GND
1, 5, 6, 16, 18, 22, 27, 28
23
20
25
19
21
24
CSADC
CSMUX
SCK
CLK
D
IN
SDO
26
F
O
LTC2408
ADCINMUXOUT
74
7
6
3
C1
0.022µF
2
4
R3
200k
C2
OPTIONAL GAIN
AND ROLL-OFF
OPTIONAL
BANDWIDTH
LIMIT
5V
R2
5.1K
3 2, 8
10µF
5V
V
REF
V
CC
V
CC
R4
5K
MAY BE REQUIRED BY OTHER
AMPLIFIERS (IS REQUIRED BY
BIPOLAR AMPLIFIERS)
R1
5.1k
+
LTC1050
24-BIT
Σ ADC
Figure 26. Inserting Gain Between the Multiplexer and the ADC Input
29
LTC2404/LTC2408
noise bandwidth of the system to 6Hz. The noise band-
width of the LTC2408 without any input bandwidth lim-
iting is approximately 150Hz. A roll-off at 1500Hz
eliminates all higher order images of the base bandwidth
of 6Hz. In the example shown, the optional bandwidth-
limit
ing filter has a –3dB point at 1450Hz. This filter can be
inserted after the multiplexer provided that higher source
impedance prior to the multiplexer does not reduce the
3dB frequency, extending settling time, and resulting in
charge sharing between samples. The settling time of this
filter to 20+ bits of accuracy is less than 2ms. In the pres-
ence of external wideband noise, this filter reduces the
apparent noise by a factor of 5. Note that the noise band-
width for noise developed in the amplifier is 150Hz. In the
example shown, the gain of the amplifier is set to 40, the
point at which amplifier noise gain dominates the LTC2408
noise. Input voltage range as shown is then 0V to 125mV
DC. The recommended capacitor at C2 for a gain of 40
would be 560pF.
Interfacing the LTC2404/LTC2408 to the 68HC11
Microcontroller
The listing in Figure 28 is a simple assembler routine for
the 68HC11 microcontroller. It uses PORT D, configuring
it for SPI data transfer between the controller and the
LTC2408. The program shows how to select and enable a
MUX channel and retrieve conversion data. Figure 27 shows
the simple 4-wire SPI connection.
APPLICATIONS INFORMATION
WUU
U
LTC2408
CLK
SCK
SD0
CSADC
CSMUX
D
IN
19
25
24
23
20
21
68HC11
24048 F27
SCK (PD4)
MISO (PD2)
SS (PD5)
MOSI (PD3)
Figure 27. Connecting the LTC2408 to a
68HC11 MCU Using the SPI Serial Interface
T
he code begins by declaring variables and allocating four
memory locations to store the 32-bit conversion result
and a fifth location to store the MUX channel address. This
is followed by initializing PORT D’s SPI configuration. The
program then enters the main sequence. It begins by
sending the MUX channel data. It then activates the
LTC2408’s serial interface by setting the SS output low,
sending a logic low to CSADC/CSMUX. This also activates
the selected MUX channel. It next waits in a loop for a logic
low on the data line, signifying end-of-conversion. After
the loop is satisfied, four SPI transfers are completed,
retrieving the conversion. The main sequence ends by
setting SS high. This places the LTC2408’s serial interface
in a high impedance state and initiates another conver-
sion. The program in Figure 30 modifies the MUX channel
selection routine in Figure 28’s listing for selection of 16
channels. Figure 29 shows the connections between the
LTC1391, LTC2408 and the 68HC11 controller.
**********************************************************
**
* This example program loads multiplexer channels selection data into *
* the LTC2408’s internal MUX and then transfers the LTC2408’s 32-bit *
* output conversion result to four consecutive 8-bit memory locations. *
**
**********************************************************
*
***************************************
* 68HC11 register definitions *
***************************************
*
PORTD EQU $1008 Port D data register
* “ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
DDRD EQU $1009 Port D data direction register
SPCR EQU $1028 SPI control register
* “SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPSR EQU $1029 SPI status register
* “SPIF,WCOL, - ,MODF; - , - , - , - “
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
*
* RAM variables to hold the LTC2408’s 32 conversion result
*
30
LTC2404/LTC2408
APPLICATIONS INFORMATION
WUU
U
DIN1 EQU $00 This memory location holds the LTC2408’s bits 31 - 24
DIN2 EQU $01 This memory location holds the LTC2408’s bits 23 - 16
DIN3 EQU $02 This memory location holds the LTC2408’s bits 15 - 08
DIN4 EQU $03 This memory location holds the LTC2408’s bits 07 - 00
MUX EQU $04 This memory location holds the MUX address data
*
***************************************
* Start GETDATA Routine *
***************************************
*
ORG $C000 Program start location
* LDS $CFFF Top of C page RAM, beginning location of stack
INIT1 LDAA #$2F -,-,1,0;1,1,1,1
* -, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set
LDAA #$38 -,-,1,1;1,0,0,0
STAA DDRD SS* , SCK, MOSI are configured as Outputs
* MISO, TxD, RxD are configured as Inputs
* DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA #$50
STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0
* and the clock rate is E/2
* (This assumes an E-Clock frequency of 4MHz. For higher
* E-Clock frequencies, change the above value of $50 to a
* value that ensures the SCK frequency is 2MHz or less.)
GETDATA PSHX
PSHY
PSHA
LDX #$0 The X register is used as a pointer to the memory
* locations that hold the conversion data
LDY #$1000
*
*******************************
* The next routine sends data to the *
* LTC2408 an sets its MUX channel *
*******************************
*
LDAA $MUX Retrieve MUX address
ORAA #$08 Set the MUX’s ENABLE bit
STAA SPDR Transfer Accum. A contents to SPI register to initiate
* serial transfer
WAITMUX LDAA SPSR Get SPI transfer status
BPL WAITMUX If the transfer is not finished, read status
*
***************************************
* Enable the LTC2408 *
***************************************
*
BCLR PORTD,Y %00100000 This sets the SS* output bit to a logic
* low, selecting the LTC2408
*
***************************************
* The next short loop waits for the *
* LTC2408’s conversion to finish before *
* starting the SPI data transfer *
***************************************
*
CONVEND LDAA PORTD Retrieve the contents of port D
ANDA #%00000100 Look at bit 2
* Bit 2 = Hi; the LTC2408’s conversion is not
* complete
* Bit 2 = Lo; the LTC2408’s conversion is complete
BNE CONVEND Branch to the loop’s beginning while bit 2 remains
* high

LTC2404IG#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 24-Bit Power 4/Ch Delta-Sigma ADC
Lifecycle:
New from this manufacturer.
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