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FT25H04S-RT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
Fremont Micro Devices Preliminary FT25H04/02
© 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25H04/02-page13
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip
Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence:
CS# goes lowSend Write Enable commandCS# goes high.
Figure1. Write Enable Sequence Diagram
CS#
SCLK
SI
SO
01234567
06H
Command
High-Z
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable
command sequence: CS# goes lowSend Write Disable commandCS# goes high. The WEL bit is reset by
following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector
Erase, Block Erase and Chip Erase commands.
Figure2. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
01234567
04H
Command
High-Z
7.3. Read Status Register (RDSR) (05H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register
may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When
one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending
a new command to the device. It is also possible to read the Status Register continuously.
Fremont Micro Devices Preliminary FT25H04/02
© 2014 Fremont Micro Devices Inc. Confidential Rev1.1 DS25H04/02-page14
Figure3. Read Status Register Sequence Diagram
CS#
SCLK
SI
SO
0123456789
05H
Command
S7~S0 out
10 11
High-Z
MSB
151412 13
7654321076543210
S7~S0 out
7
MSB
7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the
Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch
(WEL).
The Write Status Register (WRSR) command has no effect on S6, S5, S1 and S0 of the Status Register.
CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the Write Status
Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status
Register cycle (whose duration is t
W
) is initiated. While the Write Status Register cycle is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle
is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect
(BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table1.1
and 1.2. The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP) bit, the
Write Status Register (WRSR) command allows the user to set the Status Register Write Disable (SRWD) bit
to 1. The Status Register Write Disable (SRWD) bit allow the device to be put in another Software Protected
Mode. Once the SRWD bit is set to 1, the Write Status Register (WRSR) command is not executed, and the
SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
Figure4. Write Status Register Sequence Diagram
CS#
SCLK
SI
SO
0123456789
01H
Command
Status Register in
10 11
High-Z
MSB
151412 13
76543210
7.5. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being
Fremont Micro Devices Preliminary FT25H04/02
© 2014 Fremont Micro Devices Inc. Confidential Rev1.1 DS25H04/02-page15
latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO,
each bit being shifted out, at a Max frequency f
R
, during the falling edge of SCLK. The first byte addressed
can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out. Therefore, the whole memory can be read with a single Read Data Bytes (READ)
command. During an Erase, Program or Write cycle, Read Data Byte (READ) command will be rejected
without affecting the cycle in progress.
Figure5. Read Data Bytes Sequence Diagram
CS#
SCLK
SI
SO
0123456789
03H
Command
24-bit address(A23:A0)
MSB
Data Out1
10 11 3128 29 302724 25 26 3936 37 383532 33 34 40
High-Z
76543210
23 22 21 20 19
76543210
MSB
Data Out2
7.6. Read Data Bytes At Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is
followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of
SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency f
C
, during the falling edge of SCLK. The first byte address can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure6. Read Data Bytes at Higher Speed Sequence Diagram
CS#
SCLK
SI
SO
0123456789
0BH
Command
24-bit address(A23:A0)
10 11 3128 29 302724 25 26
High-Z
23 22 21 20 19
76543210
MSB
MSB
3936 37 383532 33 34
76543210
Dummy Byte
Data Out1
4744 45 464340 41 42
76543210
Data Out2
5552 53 545148 49 50
76543210
Data Out3
MSB
CS#
SCLK
SI
SO
7.7. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command
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FT25H04S-RT

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IC FLASH 4M SPI 120MHZ 8SOP
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