Fremont Micro Devices Preliminary FT25H04/02
© 2014 Fremont Micro Devices Inc. Confidential Rev1.0 DS25H04/02-page8
4. DEVICE OPERATION
The FT25H04/02 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported.
Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
5. DATA PROTECTION
The FT25H04/02 provide the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The
WEL bit will return to reset by the following situation:
Power-Up
Write Disable (WRDI)
Write Status Register (WRSR)
Page Program (PP)
Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode:
SRWD=0, the Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be
read but not change
SRWD=1, the Write Status Register (WRSR) instruction is no longer accepted for execution and the
SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
Table1.1 FT25H04 Protected Area Sizes
Status bit
BP2 BP1 BP0
Protect level Protect Block
0 0 0 0(none) None
0 0 1 1 (1 block) Block 7
0 1 0 2 (2 blocks) Block 6-7
0 1 1 3 (4 blocks) Block 4-7
1 0 0 4 (8 blocks) All
1 0 1 5 (All) All
1 1 0 6 (All) All
1 1 1 7 (All) All
