Automotive 3-Phase BLDC Controller
and MOSFET Driver
A3930 and
A3931
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Table 3. INPUT LOGIC
MODE PWM BRAKE COAST RESET Decay Mode of Operation
00111Fast PWM chop – current decay with opposite of selected drivers ON
01111Fast Peak current limit – selected drivers ON
10111Slow PWM chop – current decay with both low-side drivers ON
11111Slow Peak current limit – selected drivers ON
X X 0 1 1 n/a Brake mode - All low-side gates ON
X X X 0 1 X Coast mode - All gates OFF
XXXX0XSleep mode – All gates OFF, low power state, 5 V OFF
*X indicates “don’t care”
Table 2. Commutation Truth Table*
Device H1 H2 H3 DIR GLA GLB GLC GHA GHB GHC SA SB SC
Both 1 0 1 1001100High Z Low
Both 1 0 0 1001010ZHigh Low
Both 1 1 0 1100010LowHigh Z
Both 0 1 0 1100001LowZHigh
Both 0 1 1 1010001ZLowHigh
Both 0 0 1 1010100High Low Z
A3930 0 0 0 X 0 0 0 0 0 0 Z Z Z
A3931 0 0 0 X 0 1 1 1 0 0 High Low Low
Both 1 1 1 X 0 0 0 0 0 0 Z Z Z
Both 1 0 1 0100001LowZHigh
Both 1 0 0 0010001ZLowHigh
Both 1 1 0 0010100High Low Z
Both 0 1 0 0001100High Z Low
Both 0 1 1 0001010ZHigh Low
Both 0 0 1 0100010LowHigh Z
*X indicates “don’t care,” Z indicates high impedance state
Table 1. Fault Action Table
FF1 FF2 Fault
Action*
ESF = 0 ESF = 1
0 0 Undervoltage Disable Disable
0 0 Overtemperature No Action No Action
0 0 Logic Fault Disable Disable
1 0 Short to ground No Action Disable
1 0 Short to supply No Action Disable
1 0 Shorted motor winding No Action Disable
0 1 Low load current No Action No Action
1 1 None No Action No Action
*Disable indicates that all gate outputs are low and all MOSFETs are
turned off.
Automotive 3-Phase BLDC Controller
and MOSFET Driver
A3930 and
A3931
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Power
All supply connections to the A3930/A3931 should have capaci-
tors mounted between the supply pins and the ground pin. These
capacitors will provide the transient currents which occur during
switching and decouple any voltage transients on the pin from the
main supply.
VBB Decouple with at least a 100 nF ceramic capacitor mounted
between the VBB pin and the AGND pin. A larger electrolytic
capacitor, typically 10 F, in parallel with the ceramic capacitor
is also recommended.
VREG Supplies current for the gate-drive circuit. As the gates
are driven high, they require current from an external capacitor
connected to VREG to support the transients. This capacitor
should be placed as close as possible to the VREG pin with the
ground connection close to the AGND pin. Its value should be at
least 20 times larger than the bootstrap capacitor. The capacitor
should have a very low series resistance (ESR) and inductance
(ESL) to avoid large voltage drops during the initial transient.
The optimum capacitor type is a high quality ceramic such as
X7R. However, when the required capacitance is too large, an
aluminium electrolytic capacitor may be used, with a smaller
ceramic capacitor (100 nF) in parallel.
V5 When the 5V regulator is used with an external pass transistor
to provide power to other circuits, a 10 F decoupling capacitor
should be connected between the V5 pin and AGND as close to
the pins as possible. If an electrolytic capacitor is used, then a
100 nF ceramic capacitor should be added in parallel. To improve
stability, a 100 nF capacitor also should be connected between
the V5BD pin and AGND. If 5V is not required for external
circuits, the external pass transistor may be omitted, but in that
case, V5 must connected directly to V5BD and decoupled with at
least a 220 nF capacitor between V5 and AGND.
AGND The A3930/A3931 has a single ground connection at the
AGND pin. The design ensures that only the operating current
for the controller stage passes through this pin. The charge and
discharge current for the external FETs does not pass though this
pin. The AGND pin is the ground reference for the current trip
threshold, the V
DS
monitor threshold, and the timing components.
It should therefor be kept as quiet as possible. A suggested ground
connection scheme is described in the layout section below.
Power Dissipation In applications where a high ambient tem-
perature is expected the on-chip power dissipation may become
a critical factor. Careful attention should be paid to ensure the
operating conditions allow the A3930/A3931 to remain in a safe
range of junction temperature.
The power consumed, P
TOT
, by the A3930/A3931 can be esti-
mated using the following formulas:
P
TOT
= P
BIAS
+ P
CPUMP
+ P
SWITCHING
,
P
BIAS
= V
BB
× I
BB
,
where I
BB
is 3 mA, typical, and
P
CPUMP
= (2 × V
BB
V
REG
) × I
AV
where V
BB
< 15 V, or
P
CPUMP
= (V
BB
V
REG
) × I
AV
where V
BB
> 15 V, and
I
AV
= Q
GATE
× N × f
PWM
,
P
SWITCHING
= Q
GATE
× V
REG
× N × f
PWM
× Ratio
where N = 2 for slow decay, or N = 4 for fast decay, and
Ratio = 10 / (R
GATE
+ 10)
Bootstrap Capacitors
Bootstrap Capacitor Selection The value for C
BOOT
must
be correctly selected to ensure proper operation of the device. If
the value is too large, time will be wasted charging the capacitor,
resulting in a limit on the maximum duty cycle and PWM
frequency. If the value is too small, there can be a large voltage
drop at the time when the charge is transferred from C
BOOT
to the
MOSFET gate.
To keep the voltage drop small, Q
BOOT
Q
GATE
. A factor of 20 is
a reasonable value. To calculate C
BOOT
, the following formulas
can be used:
Q
BOOT
= C
BOOT
× V
BOOT
,
= Q
GATE
× 20,
therefore
C
BOOT
= Q
GATE
× 20 / V
BOOT
The voltage drop on the Cx pin as the MOSFET is being turned
on can be approximated by:
V = Q
GATE
/ C
BOOT
Bootstrap Charging It is good practice to ensure that the high-
side bootstrap capacitor, CBOOT, is completely charged before a
Applications Information
Automotive 3-Phase BLDC Controller
and MOSFET Driver
A3930 and
A3931
15
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
high-side PWM cycle is requested. The minimum time required
to charge the capacitor is approximated by:
t
CHARGE(min)
C
BOOT
× V /250 mA
At power-on, and when the drivers have been disabled for a long
time, the CBOOT may be completely discharged. In these cases,
V can be considered to be the full high-side drive voltage,
12 V. Otherwise, V is the amount of voltage dropped during the
charge transfer, which should be 400 mV or less. The capacitor is
charged whenever the Sx pin is pulled low via a GLx PWM cycle,
and current flows from VREG through the internal bootstrap
diode circuit to CBOOT.
Bootstrap Charge Monitor The A3930 and A3931 provide
automatic bootstrap capacitor charge management. The boot-
strap capacitor voltage for each phase, V
BOOTx
, is continuously
checked to ensure that it is above the bootstrap undervoltage
threshold, V
BOOTUV
. If V
BOOT
drops below this threshold, the
A3930 and A3931 will turn on the necessary low-side FET until
the V
BOOT
exceeds V
BOOTUV
plus the hysteresis, V
BOOTUVHys
.
The minimum charge time is typically 7 s, but may be longer for
very large values of the bootstrap capacitor (C
BOOT
>1000 nF). If
V
BOOT
does not exceed V
BOOTUV
within approximately 200 s,
an undervoltage fault will be flagged, as shown in table 1.
PWM Control
The A3930 and A3931 have the flexibility to be used in many
different motor control schemes. The internal PWM control can
be used to provide fully integrated, closed-loop current control.
Alternatively, current-mode or voltage-mode control are possible
using external control circuits with either the DIR or the PWM
input pins.
Internal PWM Control The internal PWM current control
function is useful in applications where motor torque control
or simple maximum current limitation is required. However,
for motor speed control applications, it is usually better to use
external PWM control either as a closed- or open-loop system.
External PWM Control When external PWM control is used, it
is possible to completely disable the internal PWM control circuit
by connecting the RC pin to AGND.
With the internal control disabled, however, care should be taken
to avoid excessive current in the power FETs because the A3930/
A3931 will not limit the current. Short-circuit detection will still
be available in case of faults. The output of the sense amplifier is
also available, but provision must be made in the external control
circuits to ignore (blank) the transients at the switching points.
External and Internal Combined PWM Control Where
external PWM control is used but current limitation is still
required, internal PWM current control can be used at the
same time as external PWM control. To do so, usually the
internal PWM frequency is set lower than the external PWM
frequency. This allows the external PWM signal to dominate and
synchronize the internal PWM circuit. It does this by discharging
the timing capacitor, CT, when the PWM pin is low. When
internal and external PWM control are used together, all control
features of the A3930/A3931 are available and active, including:
dead time, current comparator, and comparator blanking.
PWM Frequency Should be set high enough to avoid any
audible noise, but low enough to ensure adequate charging of the
boot capacitor, CBOOT. The external resistor RT and capacitor
CT, connected in parallel from the RC pin to AGND, set the
PWM frequency to approximately:
f
OSC
1 / (R
T
C
T
+ t
BLANK
+ t
DEAD
) .
R
T
should be in the range of 5 to 400 k.
PWM Blank The timing capacitor, CT, also serves as the
means to set the blank time duration. t
BLANK
. At the end of the
PWM off-cycle, a high-side gate selected by the commutation
logic turns on. At this time, large current transients can occur
during the reverse recovery time of the intrinsic source drain
body diodes of the external power MOSFETs. To prevent false
tripping of the current-sense comparator, the output of the current
comparator is ignored during the blank time.
The length of t
BLANK
is different for internal versus external
PWM. It is set by the value of the timing capacitor, CT, according
to the following formulas:
for internal PWM: t
BLANK
(s) = 1260 × C
T
(F), and
for external PWM: t
BLANK
(s) = 2000 × C
T
(F) .
A nominal C
T
value of 680 pF will give a blanking time of 1.3 s
for external PWM and 860 ns for internal PWM. The user must
ensure that C
T
is large enough to cover the current-spike duration.

A3930KJP-T

Mfr. #:
Manufacturer:
Description:
IC MOTOR DRIVER 5.5V-50V 48LQFP
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New from this manufacturer.
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