Automotive 3-Phase BLDC Controller
and MOSFET Driver
A3930 and
A3931
16
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Note that this blank time is only used to mask the internal cur-
rent comparator. If the current sense amplifier output, CSOUT,
is being used in an external PWM control circuit, then it will
be necessary to externally generate a blank time for that control
loop.
Dead Time The potential for cross-conduction occurs with
synchronous rectification, direction changes, PWM, or after a
bootstrap capacitor charging cycle. To prevent cross-conduction
in any phase of the power FET bridge, it is necessary to have a
dead-time delay, t
DEAD
, between a high- or low-side turn-off and
the next turn-on event. t
DEAD
is in the range of between 96 ns and
6.3 s, and is set by the value of a resistor, RDEAD, between the
RDEAD pin and the GND pin. The maximum dead time of typi-
cally 6s can be set by leaving the RDEAD pin unconnected, or
connected to the V5 pin.
At 25°C, the value of t
DEAD
(s) can be approximated by:
t
DEAD(nom)
0.1 + 33 / (5 + I
DEAD
),
I
DEAD
= 2000 / R
DEAD
where I
DEAD
is in A, and R
DEAD
is between 5 and 400 k. The
greatest accuracy is obtained with values of R
DEAD
between
10 and 100 k.
The choice of power MOSFET and external series gate resistance
determines the selection of RDEAD. The dead time should be
made long enough to cover the variation of the MOSFET gate
capacitance and the tolerances of the series gate resistance, both
external and internal to the A3930/A3931.
Synchronous Rectification To reduce power dissipation in
the external MOSFETs, the A3930/A3931 control logic turns
on the appropriate low-side and high-side driver during the load
current recirculation PWM-off cycle. Synchronous rectification
allows current to flow through the FET selected by the MODE
pin setting during the decay time, rather than through the source-
drain body diode. The body diodes of the recirculating power
FETs conduct only during the dead time that occurs at each PWM
transition. For internal current control using fast decay mode,
reversal of load current is prevented by turning off synchronous
rectification when a zero current level is detected. For external
PWM control using fast decay mode, the load current will not be
limited to zero but will rise to the set current limit in the reverse
direction before disabling synchronous rectification.
Braking. The A3930 and A3931 provide dynamic braking by
forcing all low-side MOSFETs on, and all high-side MOSFETs
off. This effectively short-circuits the back EMF of the motor,
which forces a reverse current in the windings, and creating a
breaking torque.
During braking, the load current can be approximated by:
I
BRAKE
V
BEMF
/ R
LOAD
Because the load current does not flow through the sense resistor,
RSENSE, during a dynamic brake, care must be taken to ensure
that the power MOSFET maximum ratings are not exceeded.
It is possible to apply a PWM signal to the BRAKE input to
limit the motor braking current. However, because there is
no measurement of this current, the PWM duty cycle must be
determined for each set of conditions. Typically the duty cycle
of such a brake PWM input would start at a value which limits
the current and then drops to 0%, that is, BRAKE goes to low, to
hold the motor stationary.
Setting RESET = 1 and COAST = 0 overrides BRAKE and turns
all motor bridge FETs off, coasting the motor.
Driving a Full-Bridge. The A3930 and A3931 may be used
to drive a full-bridge (for example, a brush DC motor load) by
hard-wiring a single state for the Hall inputs and leaving the
corresponding phase driver outputs floating. For example, with a
configuration of H1 = H2 = 1, and H3 = 0, the outputs CC, GHC,
SC, and GLC would be floated, according to the commutation
truth table, table3, which indicates a state of high-impedence (Z)
for SC with that Hall input configuration. The DIR input
controls the motor rotation, while the PWM and MODE
inputs control the motor current behavior, as described in the
input logic table, table 3.
Figure 2. Internal PWM RC Timing
V
RCH
RC
0
+V
V
RCL
t
RC
t
BLANK
t
OSC
GHx
GLx
Current
Trip Points
t
DEAD
t
DEAD
Note: For reasons of
clarity, t
DEAD
is shown
exaggerated.
