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A3930KJP-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Automotive 3-Phase BLDC Controller
and MOSFET Driver
A3930 and
A3931
19
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VDRAIN
19 V
Supplies
19 V
20 V
VBB
19 V
19 V
20 V
V5
6 V
V5BD
10 V
CP1
18 V
CP2
H1
H2
H3
3 k7
8 V 8.5 V
100 k7
V5
Hall Sensor Inputs
COAST
ESF
BRAKE
DIR
PWM
MODE
3 k7
8 V 8.5 V
Logic Inputs
RC
1 k7
8 V
8.5 V
Oscillator RC Pin
V5
REF
3 k7
8 V
8.5 V
REF
VDSTH
1 k7
8 V
8.5 V
V
DS
Monitor Threshold Input
40 k7
FF1
FF2
8 V
Fault Output
100 7
8 V
RDEAD
100 7
8 V
8.5 V
RDEAD
2 V
RESET
3 k7
6 V 6 V
Reset Input
50 k7
TACHO
DIRO
8 V
Logic Output
100 7
8 V
V5
CSN
CSP
22V
22V
VREG
4 k7
4 k7
72 k7
76k
8.5 V
8.5 V
CSOUT
2V
32.4 k7
4.6 k7
160μA
160μA
Sense Amplifier
Cx
18 V
18 V
GHx
Sx
GLx
LSS
19 V
20 V
18 V
18 V
20 V
18 V
VREG
18 V
Gate Drive Outputs
Figure 4. Input and Output Structures
Automotive 3-Phase BLDC Controller
and MOSFET Driver
A3930 and
A3931
20
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
JP Package
Pin-out Diagrams
Bootstrapped
High-Side Drives
Hall
Control
Logic
Current
Sense
Charge
Pump
Low
Side
Drives
43
44
45
46
47
48
42
41
16
15
14
13
17
18
37
38
39
40
7
8
9
10
11
12
6
5
1
2
3
4
30
29
28
27
26
25
31
32
36
35
34
33
22
21
24
23
20
19
RDEAD
TEST
RC
MODE
PWM
NC
AGND
CP1
CP2
DIRO
VBB
COAST
NC
NC
LSS
NC
ESF
VREG
FF2
FF1
TACHO
BRAKE
DIR
H1
H2
H3
RESET
NC
V5BD
V5
GHA
SA
CB
GHB
SB
CC
GHC
SC
GLB
GLA
GLC
CA
CSP
CSN
REF
CSOUT
VDSTH
VDRAIN
Number Name Description
1 N.C. No connection
2 RESET Control for sleep mode
3 V5BD 5V regulator base drive
4 V5 5V regulator reference
5 FF2 Fault flag 2
6 FF1 Fault flag 1
7 TACHO Speed output
8 BRAKE Brake input
9 DIR Direction control input
10 H1 Hall sensor input
11 H2 Hall sensor input
12 H3 Hall sensor input
13 N.C. No connection
14 PWM Control input
15 MODE Decay control input
16 RC PWM oscillator control input
17 TEST Test pin; tie to AGND
18 RDEAD Dead time setting
19 CSOUT Current sense output
20 REF Current limit setting
21 CSN Current sense input –
22 CSP Current sense input +
23 VDSTH Fault threshold voltage
24 VDRAIN High-side drain voltage sense
Number Name Description
25 SC Motor connection phase C
26 GHC High-side gate drive phase C
27 CC Bootstrap capacitor phase C
28 SB Motor connection phase B
29 GHB High-side gate drive phase B
30 CB Bootstrap capacitor phase B
31 SA Motor connection phase A
32 GHA High-side gate drive phase A
33 CA Bootstrap capacitor phase A
34 GLC Low-side gate drive phase C
35 GLB Low-side gate drive phase B
36 GLA Low-side gate drive phase A
37 N.C. No connection
38 LSS Low-side source
39 ESF Enable stop on fault input
40 VREG Gate drive supply output
41 AGND Analog ground
42 CP1 Pump capacitor
43 CP2 Pump capacitor
44 DIRO Direction output
45 VBB Supply voltage
46 COAST Coast input
47 N.C. No connection
48 N.C. No connection
– Pad Thermal dissipation, tie to AGND
Terminal List Table
Automotive 3-Phase BLDC Controller
and MOSFET Driver
A3930 and
A3931
21
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package JP, 48-pin LQFP with Exposed Thermal Pad
Copyright ©2006-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its
use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
21
48
A
Exposed thermal pad (bottom surface)
Terminal #1 mark area
B
B
A
7º
0º
C
SEATING
PLANE
C0.08
48X
GAGE PLANE
SEATING PLANE
1.60 MAX
0.50
5.00 8.60
0.30
1.70
8.60
5.00
For Reference Only
(reference JEDEC MS-026 BBCHD)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1.40 ±0.05
0.10 ±0.05
0.22 ±0.05
9.00 ±0.20
9.00 ±0.20 7.00 ±0.20
7.00 ±0.20
0.50
PCB Layout Reference View
C
0.25
(1.00)
0.60 ±0.15
4° ±4
0.15
+0.05
–0.06
5.00±0.04
5.00±0.04
C
Reference land pattern layout (reference IPC7351
QFP50P900X900X160-48M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
48
2
1
C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

A3930KJP-T

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Buy A3930KJP-T
Manufacturer:
Description:
IC MOTOR DRIVER 5.5V-50V 48LQFP
Lifecycle:
New from this manufacturer.
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