NCV7718B
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16
Driver Control
The NCV7718B has the flexibility of controlling each
driver through the 16 bit SPI frame (Bits 12−1) and the logic
combination required for bridge control is defined in
Figure 14.
HBENx
HBCNFx
OUTx
VS
HSx
LSx
HBENx HBCNFx OUTx
0 ‘X’ OUTx in High Impedance State
1 0 HSx Off and LSx On
1 1 HSx On and LSx Off
‘X’ = Don’t Care
Figure 14. Bridge Control Logic
The digital design insures that the high side and low side
of the same half bridge will not be active at the same time.
Thus the device self protects from a current shoot through
condition. Delays (ThsOffLsOn and TlsOffHsOn) between
the high side and low side switching are implemented for
same reasons.
Frame Detection
To maintain the data integrity, the NCV7718B has 16 bit
frame detection. A valid frame for a single CSB cycle
requires 16 bits to be clocked into SI for the initial 16 bits and
n x 8 bits thereafter. In an instance of an invalid SPI frame
the entire frame is ignored, but the previous states of the
corresponding outputs are maintained.
Daisy Chain Operation
Daisy chain communications between multiple of 8−bit
SPI compatible IC’s is possible by connection of the serial
output pin (SO) to the input of the sequential IC (SI). The
clock phase and clock polarity respect to the data must be the
same for all the devices on the chain. Figure 15 illustrates the
hardware configuration of NCV7718B daisy chained with a
n*8 bit (ie n = 2; 16 bit) SPI device. The progression of data
from the MCU through the sequential devices is also shown.
Strict adherence to the frame format illustrated in Figure 16
is required for the proper serial daisy chain operations.
