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NCV7718BDQR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
NCV7718B
http://onsemi.com
19
DEVICE PROTECTION, DIAGNOSTICS AND FAULT REPORTING
Power Up/Down Control
Each analog power pin (VS1 or VS2) powers their
respective output drivers. After a device has powered up and
the output drivers are allowed to turn on, the output drivers
will not turn off until the voltage on the supply pins is
reduced below the initial under voltage threshold, exceeds
the over voltage threshold or if shut down by either a SPI
command or a fault condition.
Internal power−up circuitry on the logic supply pin
supports a smooth turn on transition. VCC power up resets
the internal logic such that all output drivers will be off as
power is applied. All the internal counters, SI and SO along
with all the digital registers will be cleared on VCC POR.
Exceeding the under voltage lockout threshold on VCC
allows information to be input through the SPI port for turn
on control. Logic information remains intact over the entire
VS1 and VS2 voltage range.
Under Voltage Shutdown
An under voltage lockout circuit prevents the output
drivers from turning on unintentionally. This control is
provided by monitoring the voltages on the VS1, VS2 and
VCC pins. A built−in hysteresis on the under voltage
threshold is included to prevent an unknown region on the
power pins; VCC, VS1 and VS2. When the VCC goes below
the threshold, all outputs are turned off and the input and
output registers are cleared.
An under voltage condition on the VSx pins will result in
shutting off all the drivers and the status bit 14 (PSF) will be
set. The SPI port remains active during a VSx under−voltage
if proper VCC voltage is supplied. Also all driver states will
be maintained in the logic circuitry with the valid VCC
voltage. Once the input voltage VSx is above the under
voltage threshold level the drivers will return to
programmed operation and the PSF output register bit is
cleared.
Under−voltage timing diagram is provided in Figure 20.
Figure 20. Under−Voltage Timing Diagram
OUTx
LS
?
OUTx
LS
?
X
No
Fault
OUTx
LS
PSF
ALL
Z
OUTx
LS
No
Fault
³0x00
ALL
Z
VSx
Vcc
?
OUTx
HS
OUTx
HS
VSUV
VccUV
No Fault
PSF
No
Fault
0x00
OUTx VS
No
Fault
OUTx
HS
No
Fault
t
OUTx GND
OUTx GND
SI
Status
Output
State
SO
Z
NCV7718B
http://onsemi.com
20
Over Voltage Shutdown
Over voltage shutdown circuitry monitors the voltage on
the VS1 and VS2 pins, which permits a 40 V maximum.
When the Over−voltage Threshold level has been breached
on the VS1or VS2 supply input, the output bit 14 (PSF) will
be set. Additionally, if the input bit 0 (OVLO) is asserted, all
outputs will turn off. During an Over Voltage Lockout
condition the turn on/off status is maintained in the logic
circuitry. When proper input voltage levels are
re−established, the programmed outputs will turn back on.
Over−voltage shutdown can be disabled by using the SPI
input bit 0 (OVLO = 0) to run through a load dump situation.
It is highly recommended to operate the part with OVLO bit
asserted to ensure that the drivers remain off during a load
dump scenario.
The table below describes the driver status when
enabling/disabling the over voltage lock out feature during
normal and overvoltage situations.
Table 3. OVER−VOLTAGE LOCK OUT (OVLO)
OVLO Input
Bit
VSx OVLO
Condition
Output Data Bit 14 Power Supply Fail (PSF) Status OUTx Status
0 0 ‘0’ Not in Overvoltage Outputs Unchanged
0 1 ‘1’
(Clears when VSx within Operating Range)
In Overvoltage ³ Outputs Unchanged
1 0 ‘0’ Not in Overvoltage Outputs Unchanged
1 1 ‘1’
(Clears when VSx within Operating Range)
All Outputs Off (Remain off until VSx is out
of OVLO)
Over−voltage timing diagram is provided in Figure 21.
Figure 21. Over−Voltage Timing Diagram
?
?
OUTx
ON
PSF
ALL
Z
VSx
VSOV
PSF
No
Fault
No
Fault
t
SI
Status
Output
State
SO
OUTx ON
OVLO=0
X
OUTx
ON
No
Fault
No
Fault
OUTx
ON
OUTx ON
OVLO=1
No
Fault
VSOV
PSF
PSF
OUTx
ON
OUTx
ON
No
Fault
OUTx
OFF
No
Fault
OUTx Z
NCV7718B
http://onsemi.com
21
Over Current Detection and Shutdown
The NCV7718B offers over current shutdown protection
on the OUTx pins by monitoring the current on the high side
and low side drivers. If the over current threshold is
breached, the corresponding output is latched off (HS and
LS driver is latched off) after the specified shutdown time,
TdOc. Upon over current shutdown, the serial output bit
OCS will be set and the corresponding HBx[1:0] will be
changed to “01” to denote a high power dissipation state.
Devices can be turned back on via the SPI port once the OCS
condition is cleared by setting the SRR to ‘1’ on the next SPI
command. The event triggering the over current shutdown
condition must be resolved prior to clearing the OCS bit to
avoid repetitive stress on the drivers. Failure to do so may
result in non reversible fatal damage.
The SO data OCS shown on Figure 22 corresponds to both
the global SO bit #15 and the HBx OCS encoding state ‘01’.
Note: high currents could cause a high rise in die
temperature. Devices will turn off if the die temperature
exceeds the thermal shutdown temperature.
Figure 22. Over−Current Timing Diagram
OUTx
ON
OCS
IsdSxx
t
SI
Status
Output
State
SO
OUTx ON
SRR=0
OUTx
ON
No
Fault
OUTx ON
SRR=1
OUTx
ON
OUTx Z
Output
Current
OUTx
ON
No
Fault
No
Fault
TdOc
OCS
OUTx Z
TdOc
OUTx
ON
No
Fault
No
Fault
OUTx
ON
OCS
OCS
OCS
Under Load Detection
The under−load detection is accomplished by monitoring
the current from the low side drivers and one global output
bit is used for under load fault reporting. A minimum load
current (IuldLS − this is the maximum open circuit detection
threshold) is required when the drivers are turned on to avoid
an under−load condition. If the under−load detection
threshold has been breached longer than the specified
under−load timer (TdUld), the ULD output bit is set to ‘1’.
Furthermore, if the Under−Load Detection Shutdown
Control (ULDSC bit # 13) input bit is set then the offending
half−bridge output will be turned off (HS and LS on the
driver will be latched off).
There is only one global under load timer for all the
drivers. If the TdUld timer is already activated due to one
under load, any subsequent under load delays will be the
remainder of the TdUld timer.
Table 4. UNDER−LOAD DRIVER STATUS
ULDSC Input
Bit 13
OUTx ULD
Condition
Output Data Bit Under Load Detect Status OUTx Status
0 0 ‘0’ Unchanged
0 1
‘1’
(Need SRR to reset)
Unchanged
1 0 ‘0’ Unchanged
1 1 ‘1’ (Need SRR to reset) OUTx Latches off (Need SRR to reset)
The ULD SO data provided in the under load timing diagram in Figure 24 reflects the global ULD SO bit #13 and the HBx
ULD encoding state ‘10’.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

NCV7718BDQR2G

Mfr. #:
Buy NCV7718BDQR2G
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers HALF BRIDGE DRIVER
Lifecycle:
New from this manufacturer.
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