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ADSP-2101BG-100

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
ADSP-21xx
–22–
REV.
SUPPLY CURRENT & POWER (ADSP-2111)
Parameter Test Conditions Min Max Unit
I
DD
Supply Current (Dynamic)
1
@ V
DD
= max, t
CK
= 50 ns
2
60 mA
@ V
DD
= max, t
CK
= 60 ns
2
52 mA
@ V
DD
= max, t
CK
= 76.9 ns
2
46 mA
I
DD
Supply Current (Idle)
1, 3
@ V
DD
= max, t
CK
= 50 ns 18 mA
@ V
DD
= max, t
CK
= 60 ns 16 mA
@ V
DD
= max, t
CK
= 76.9 ns 14 mA
NOTES
1
Current reflects device operating with no output loads.
2
V
IN
= 0.4 V and 2.4 V.
3
Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V
DD
or GND.
For typical supply current (internal power dissipation) figures, see Figure 17.
SPECIFICATIONS (ADSP-2111)
Figure 17. ADSP-2111 Power (Typical) vs. Frequency
POWER (P
I
DLE
) – mW
POWER, IDLE
1,2
50
30
40
80
60
70
90
100
201817161514 19
100mW
70mW
50mW
1/ t
CK
– MHz
40mW
55mW
80mW
POWER, IDLE
n
MODES
3
40
30
35
55
45
50
60
65
70
IDLE;
32mW
34mW
IDLE 16;
IDLE 128;
70mW
55mW
201817161514 19
36mW
38mW
POWER (P
IDLE
n
) – mW
1/ t
CK
– MHz
VALID FOR ALL TEMPERATURE GRADES.
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2
IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER V
DD
OR GND.
3
MAXIMUM POWER DISSIPATION AT V
DD
= 5.0V DURING EXECUTION OF
IDLE
n
INSTRUCTION.
POWER (P
INT
) – mW
201817161514 19
1
/ t
CK
– MHz
330mW
260mW
200mW
250mW
200mW
155mW
POWER, INTERNAL
1
190
150
170
250
210
230
270
310
290
330
V
DD
=
5.5V
V
DD
=
5.0V
V
DD
=
4.5V
V
DD
=
5.5V
V
DD
=
5.0V
V
DD
=
4.5V
V
DD
=
5.0V
C
ADSP-21xx
REV.
–23–
POWER DISSIPATION EXAMPLE
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × V
DD
2
× f
C = load capacitance, f = output switching frequency.
Example:
In an ADSP-2111 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
Each address and data pin has a 10 pF total load at the pin.
•
The application operates at V
DD
= 5.0 V and t
CK
= 50 ns.
Total Power Dissipation = P
INT
+ (C × V
DD
2
× f )
P
INT
= internal power dissipation (from Figure 17).
(C × V
DD
2
× f ) is calculated for each output:
# of
Output Pins × C × V
DD
2
× f
Address, DMS 8 × 10 pF × 5
2
V × 20 MHz = 40.0 mW
Data,
WR 9 × 10 pF × 5
2
V × 10 MHz = 22.5 mW
RD 1 × 10 pF × 5
2
V × 10 MHz = 2.5 mW
CLKOUT 1 × 10 pF × 5
2
V × 20 MHz = 5.0 mW
70.0 mW
Total power dissipation for this example = P
INT
+ 70.0 mW.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
T
AMB
= T
CASE
– (PD × θ
CA
)
T
CASE
= Case Temperature in °C
PD = Power Dissipation in W
θ
CA
= Thermal Resistance (Case-to-Ambient)
θ
JA
= Thermal Resistance (Junction-to-Ambient)
θ
JC
= Thermal Resistance (Junction-to-Case)
Package θ
JA
θ
JC
θ
CA
PGA 35°C/W 18°C/W 17°C/W
PQFP 42°C/W 18°C/W 23°C/W
SPECIFICATIONS (ADSP-2111)
CAPACITIVE LOADING
Figures 18 and 19 show capacitive loading characteristics for the
ADSP-2111.
C
L
– pF
25 1501251007550
RISE TIME (0.8V - 2.0V) – ns
14
2
6
4
8
10
12
V
DD
= 4.5V
Figure 18. Typical Output Rise Time vs. Load Capacitance, C
L
(at Maximum Ambient Operating Temperature)
C
L
– pF
25 100 12550 75 150
VALID OUTPUT DELAY OR HOLD – ns
+10
–2
–6
–4
+4
+2
+6
+8
+12
NOMINAL
V
DD
= 4.5V
Figure 19. Typical Output Valid Delay or Hold vs. Load
Capacitance, C
L
(at Maximum Ambient Operating Temperature)
C
ADSP-21xx
–24–
REV.
SPECIFICATIONS (ADSP-2111)
The decay time, t
DECAY
, is dependent on the capacitative load,
C
L
, and the current load, i
L
, on the output pin. It can be
approximated by the following equation:
t
DECAY
=
C
L
×0.5V
i
L
from which
t
DIS
= t
MEASURED
– t
DECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t
ENA
) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 21. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
TEST CONDITIONS
Figure 20 shows voltage reference levels for ac measurements.
Figure 20. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (t
DIS
) is the difference of t
MEASURED
and
t
DECAY
, as shown in Figure 21. The time t
MEASURED
is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
3.0V
1.5V
0.0V
2.0V
1.5V
0.8V
INPUT
OUTPUT
Figure 22. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)
2.0V
1.0V
t
ENA
REFERENCE
SIGNAL
OUTPUT
t
DECAY
V
OH
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
t
DIS
t
MEASURED
V
OL
(MEASURED)
V
OH
(MEASURED) – 0.5V
V
OL
(MEASURED) +0.5V
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
V
OH
(MEASURED)
V
OL
(MEASURED)
Figure 21. Output Enable/Disable
TO
OUTPUT
PIN
50pF
+1.5V
I
OH
I
OL
C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

ADSP-2101BG-100

Mfr. #:
Buy ADSP-2101BG-100
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16-Bit 25MIPS 5V 2 Serial Ports
Lifecycle:
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