ADSP-21xx
–34–
REV.
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
MEMORY WRITE
13 MHz 13.824 MHz 16.67 MHz 20 MHz 25 MHz
Parameter Min Max Min Max Min Max Min Max Min Max Unit
Switching Characteristic:
t
DW
Data Setup before WR High 25.5 23.2 17 12 7 ns
t
DH
Data Hold after WR High 9.2 8.1 5 2.5 0 ns
t
WP
WR Pulse Width 30.5 28.2 22 17 12 ns
t
WDE
WR Low to Data Enabled 0 0 0 0 0 ns
t
ASW
A0–A13, DMS, PMS Setup before 9.2 8.1 5 2.5 1.5
1
ns
WR Low
t
DDR
Data Disable before WR or RD Low 9.2 8.1 5 2.5 1.5
1
ns
t
CWR
CLKOUT High to WR Low 14.2 29.2 13.1 28.1 10 25 7.5 22.5 5 20 ns
t
AW
A0–A13, DMS, PMS, Setup before WR 35.7 32.2 23 15.5 8 ns
Deasserted
t
WRA
A0–A13, DMS, PMS Hold after WR 10.2 9.1 6 3.5 1 ns
Deasserted
t
WWR
WR High to RD or WR Low 33.5 31.2 25 20 15 ns
Figure 33. Memory Write
CLKOUT
A0 – A13
D
t
WRA
WR
DMS, PMS
t
WWR
t
WP
t
ASW
t
AW
t
CWR
RD
t
DH
t
DDR
t
WDE
t
DW
Frequency Dependency
(CLKIN ≤ 25 MHz)
Parameter Min Max Unit
Switching Characteristic:
t
DW
Data Setup before WR High 0.5t
CK
– 13 + w ns
t
DH
Data Hold after WR High 0.25t
CK
– 10 ns
t
WP
WR Pulse Width 0.5t
CK
– 8 + w ns
t
WDE
WR Low to Data Enabled 0
t
ASW
A0–A13, DMS, PMS Setup before WR Low 0.25t
CK
– 10
1
ns
t
DDR
Data Disable before WR or RD Low 0.25t
CK
– 10
1
ns
t
CWR
CLKOUT High to WR Low 0.25t
CK
– 5 0.25t
CK
+ 10 ns
t
AW
A0–A13, DMS, PMS, Setup before WR
Deasserted 0.75t
CK
– 22 + w ns
t
WRA
A0–A13, DMS, PMS Hold after WR
Deasserted 0.25t
CK
– 9 ns
t
WWR
WR High to RD or WR Low 0.5t
CK
– 5 ns
NOTES
1
For 25 MHz only the minimum frequency dependency formula for t
ASW
and t
DDR
= (0.25t
CK
– 8.5).
w = wait states × t
CK
.
