ADSP-21xx
–44–
REV.
TIMING PARAMETERS (ADSP-2103/2162/2164)
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
MEMORY REQUIREMENTS
The table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
ADSP-21xx
Memory Specification Timing Parameter Timing Parameter Definition
Address Setup to Write Start t
ASW
A0–A13, DMS, PMS Setup before WR Low
Address Setup to Write End t
AW
A0–A13, DMS, PMS Setup before WR Deasserted
Address Hold Time t
WRA
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup Time t
DW
Data Setup before WR High
Data Hold Time t
DH
Data Hold after WR High
OE to Data Valid t
RDD
RD Low to Data Valid
Address Access Time t
AA
A0–A13, DMS, PMS, BMS to Data Valid
