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ADSP-2101BG-100

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64
ADSP-21xx
–46–
REV.
TIMING PARAMETERS (ADSP-2103/2162/2164)
INTERRUPTS & FLAGS
Frequency
10.24 MHz Dependency
Parameter Min Max Min Max Unit
Timing Requirement:
t
IFS
IRQx
1
or FI Setup before CLKOUT Low
2, 3
44.4 0.25t
CK
+ 20 ns
t
IFH
IRQx
1
or FI Hold after CLKOUT High
2, 3
24.4 0.25t
CK
ns
Switching Characteristic:
t
FOH
FO Hold after CLKOUT High 0 ns
t
FOD
FO Delay from CLKOUT High 15 ns
NOTES
1
IRQx=IRQ0, IRQ1, and IRQ2.
2
If IRQx and FI inputs meet t
IFS
and t
IFH
setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
FLAG
OUTPUT(S)
t
FOD
IRQx
FI
t
FOH
t
IFH
t
IFS
Figure 40. Interrupts & Flags
C
ADSP-21xx
REV.
–47–
TIMING PARAMETERS (ADSP-2103/2162/2164)
BUS REQUEST/GRANT
Frequency
10.24 MHz Dependency
Parameter Min Max Min Max Unit
Timing Requirement:
t
BH
BR Hold after CLKOUT High
1
29.4 0.25t
CK
+ 5 ns
t
BS
BR Setup before CLKOUT Low
1
44.4 0.25t
CK
+ 20 ns
Switching Characteristic:
t
SD
CLKOUT High to DMS, PMS, BMS, RD, WR Disable 44.4 0.25t
CK
+ 20 ns
t
SDB
DMS, PMS, BMS, RD, WR Disable to BG Low 0 ns
t
SE
BG High to DMS, PMS, BMS, RD, WR Enable 0 ns
t
SEC
DMS, PMS, BMS, RD, WR Enable to CLKOUT High 14.4 0.25t
CK
– 10 ns
NOTES
1
If BR meets the t
BS
and t
BH
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulse width greater than 10 ns.
Section 10.2.4, “Bus Request/Grant,” of the ADSP-2100 Family User’s Manual (1st Edition, ©1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the
cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
Figure 41. Bus Request/Grant
CLKOUT
PMS, DMS
BMS, RD
WR
t
BS
BR
BG
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
BH
C
ADSP-21xx
–48–
REV.
TIMING PARAMETERS (ADSP-2103/2162/2164)
MEMORY READ
Frequency
10.24 MHz Dependency
Parameter Min Max Min Max Unit
Timing Requirement:
t
RDD
RD Low to Data Valid 33.8 0.5t
CK
– 15 + w ns
t
AA
A0–A13, PMS, DMS, BMS to Data Valid 49.2 0.75t
CK
– 24 + w ns
t
RDH
Data Hold from RD High 0 ns
Switching Characteristic:
t
RP
RD Pulse Width 43.8 0.5t
CK
– 5 + w ns
t
CRD
CLKOUT High to RD Low 19.4 34.4 0.25t
CK
– 5 0.25t
CK
+ 10 ns
t
ASR
A0–A13, PMS, DMS, BMS Setup before RD Low 12.4 0.25t
CK
– 12 ns
t
RDA
A0–A13, PMS, DMS, BMS Hold after RD Deasserted 14.4 0.25t
CK
– 10 ns
t
RWR
RD High to RD or WR Low 38.8 0.5t
CK
– 10 ns
w = wait states × t
CK.
Figure 42. Memory Read
CLKOUT
A0 – A13
D
t
RDA
RD
WR
DMS, PMS
BMS
t
RWR
t
RP
t
ASR
t
CRD
t
RDD
t
AA
t
RDH
C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P64

ADSP-2101BG-100

Mfr. #:
Buy ADSP-2101BG-100
Manufacturer:
Analog Devices Inc.
Description:
Digital Signal Processors & Controllers - DSP, DSC 16-Bit 25MIPS 5V 2 Serial Ports
Lifecycle:
New from this manufacturer.
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