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ICS1562BM-201-4

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
REG# BIT(S) BIT REF. DESCRIPTION
11 0-1 S[0]..S[1] PLL post-scaler/test mode select bits
S[1] S[0] DESCRIPTION
0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
1 1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD
output which, in turn, drives the N2 divider.
11 2 AUX_CLK When in the AUXEN clock mode, this bit controls the differential
outputs.
11 3 AUX_N1 When in the AUXEN clock mode, this bit controls the LOAD output
(and consequently the N2 output according to its programming).
When not in the AUXEN clock mode, this bit, if set to one, will over-
ride the N1 divider modulus and output the VCO frequency divided
by two [F(PLL)/2] at the LOAD output.
12 0 RESERVED Must be set to zero.
12 1 JAMPLL Tristates phase detector outputs; resets phase detector logic, and
resets R, A, M, and N2 counters.
12 2 DACRST Set to zero for normal operation. When set to one, the CLK+output
is kept high and the CLK- output is kept low. (All other device func-
tions are unaffected.) When returned to zero, the CLK+ and CLK-
outputs will resume toggling on a rising edge of the LD output
(+/- 1 CLK period). To initiate a RAMDAC reset sequence,
simply write a one to this register bit followed by a zero.
12 3 SELXTAL When set to logic 1, passes the reference frequency to the post-scaler.
15 0 ALTLOOP Controls substitution of N1 and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N1 and N2 dividers are used.
15 3 PDRSTEN Phase-detector reset enable control bit. When this bit is set, the AD3
pin becomes a transparent reset input to the phase detector.
See "Internal Feedback Operation" section for more
details on the operation of this function.
ICS1562B
10
Register Mapping - ICS1562B-201 (Serial Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562B. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
BIT(S) BIT REF. DESCRIPTION
1-4 N1[0]..N1[3] Sets N1 modulus according to this table. These bits are set to implement
a divide-by-four on power-up.
N1[3] N1[2] N1[1] N1[0] RATIO
00003
00014
00104
00115
01006
01018
01108
011110
1X0012
1X0116
1X1016
1X1120
5 RESERVED Must be set to zero.
6 JAMPLL Tristates phase detector outputs, resets phase detector logic, and resets
R, A, M, and N2 counters.
7 DACRST Set to zero for normal operations. When set to one, the CLK+ output is
kept high and the CLK- output is kept low. (All other device functions are
unaffected.) When returned to zero, the CLK+ and CLK- outputs will
resume toggling on a rising edge of the LD output (+/−1 CLK period).
To initiate a RAMDAC reset sequence, simply write a one to this register
bit followed by a zero.
8 SELXTAL When set to logic 1, passes the reference frequency to the post-scaler.
9 ALTLOOP Controls substitution of N1 and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N1 and N2 dividers are used.
10 SCEN VRAM shift clock enable bit. When logic 1, the BLANK pin can be used
to disable the LD/N2 output.
11 EXTFBKEN External PLL feedback select. When logic 1, the EXTFBK pin is used for
the phase-frequency detector feedback input.
12 PDRSTEN Phase detector reset enable control bit. When this bit is set, a high level
on the BLANK input will disable PLL locking. See "Internal Feedback
Operation" section for more details on the operation of this function.
ICS1562B
11
BIT(S) BIT REF. DESCRIPTION
13-14 S[0]..S[1] PLL post-scaler/test mode select bits.
S[1] S[0] DESCRIPTION
0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divder
drives the LOAD output which, in turn, drives the N2 divider.
1 1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD
output which, in turn, drives the N2 divider.
15 AUX_CLK When in the AUXEN clock mode, this bit controls the differential outputs.
16 AUX_N1 When in the AUXEN clock mode, this bit controls the N1 output (and
consequently the N2 output according to its programming). When not in
the AUXEN clock mode, this bit, if set to one, will override the N1 divider
modulus and output the VCO frequency divided by two [F(PLL)/2] at the
LOAD output.
17-24 N2[0]..N2[7] Sets the modulus of the N2 divider. The input of the N2 divider is the
28 N2[8] output of the N1 divider in all clock modes except AUXEN.
25-27 V[0]..V[2] Sets the gain of VCO according to this table.
V[2] V[1] V[0] VCO GAIN
(MHz/VOLT)
100 30
101 45
110 60
111 80
29-30 P[0]..P[1] Sets the gain of the phase detector according to this table.
P[1] P[0] GAIN (uA/radian)
00 0.05
01 0.15
10 0.5
11 1.5
31 RESERVED Set to zero.
32 P[2] Phase detector tuning bit. Should normally be set to one.
ICS1562B
12
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ICS1562BM-201-4

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IC VIDEO CLK SYNTHESIZER 16-SOIC
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