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ICS1562BM-201-4

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
BIT(S) BIT REF. DESCRIPTION
33-38 M[0]..M[5] M counter control bits
Modulus = value +1
39 FBKPOL External feedback polarity control bit. The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of EXTFBK
when FBKPOL=0.
40 DBLFREQ Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).
41-44 A[0]..A[3] Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for “value” underflows of the prescaler, and modulus=6
thereafter until M counter underflows.
45 RESERVED Set to zero.
46 LOADEN~ Load clock divider enable (active low). When set to logic 1, the LOAD
and LD/N2 outputs will cease toggling.
47 SKEW- Differential output duty factor adjust.
48 SKEW+
49-55 R[0]..R[6] Reference divider modulus control bits
Modulus = value + 1
56 REFPOL PLL locks to the rising edge of XTAL1 input when REFPOL=1 and to
the falling edge of XTAL1 when REFPOL=0.
SKEW+ SKEW-
0 0 Default
0 1 Reduces T
HIGH
by approximately
100 ps
1 0 Increases T
HIGH
by approximately
100 ps
1 1 Do not use
ICS1562B
13
Table 1 - “A” & “M” Divider Programming
Feedback Divider Modulus Table
A[2]..A[0]- 001 010 011 100 101 110 111 000
M[5]..M[0]
000000 7
000001 13 14
000010 19 20 21
000011 25 26 27 28
000100 31 32 33 34 35
000101 37 38 39 40 41 42
000110 43 44 45 46 47 48 49
000111 49 50 51 52 53 54 55 56
001000 55 56 57 58 59 60 61 63
001001 61 62 63 64 65 66 67 70
001010 67 68 69 70 71 72 73 77
001011 73 74 75 76 77 78 79 84
001100 79 80 81 82 83 84 85 91
001101 85 86 87 88 89 90 91 98
001110 91 92 93 94 95 96 97 105
001111 97 98 99 100 101 102 103 112
010000 103 104 105 106 107 108 109 119
010001 109 110 111 112 113 114 115 126
010010 115 116 117 118 119 120 121 133
010011 121 122 123 124 125 126 127 140
010100 127 128 129 130 131 132 133 147
010101 133 134 135 136 137 138 139 154
010110 139 140 141 142 143 144 145 161
010111 145 146 147 148 149 150 151 168
011000 151 152 153 154 155 156 157 175
011001 157 158 159 160 161 162 163 182
011010 163 164 165 166 167 168 169 189
011011 169 170 171 172 173 174 175 196
011100 175 176 177 178 179 180 181 203
011101 181 182 183 184 185 186 187 210
011110 187 188 189 190 191 192 193 217
011111 193 194 195 196 197 198 199 224
A[2]..A[0]- 001 010 011 100 101 110 111 000
M[5]..M[0]
100000 199 200 201 202 203 204 205 231
100001 205 206 207 208 209 210 211 238
100010 211 212 213 214 215 216 217 245
100011 217 218 219 220 221 222 223 252
100100 223 224 225 226 227 228 229 259
100101 229 230 231 232 233 234 235 266
100110 235 236 237 238 239 240 241 273
100111 241 242 243 244 245 246 247 280
101000 247 248 249 250 251 252 253 287
101001 253 254 255 256 257 258 259 294
101010 259 260 261 262 263 264 265 301
101011 265 266 267 268 269 270 271 308
101100 271 272 273 274 275 276 277 315
101101 277 278 279 280 281 282 283 322
101110 283 284 285 286 287 288 289 329
101111 289 290 291 292 293 294 295 336
110000 295 296 297 298 299 300 301 343
110001 301 302 303 304 305 306 307 350
110010 307 308 309 310 311 312 313 357
110011 313 314 315 316 317 318 319 364
110100 319 320 321 322 323 324 325 371
110101 325 326 327 328 329 330 331 378
110110 331 332 333 334 335 336 337 385
110111 337 338 339 340 341 342 343 392
111000 343 344 345 346 347 348 349 399
111001 349 350 351 352 353 354 355 406
111010 355 356 357 358 359 360 361 413
111011 361 362 363 364 365 366 367 420
111100 367 368 369 370 371 372 373 427
111101 373 374 375 376 377 378 379 434
111110 379 380 381 382 383 384 385 441
111111 385 386 387 388 389 390 391 448
Notes:
To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values.
Follow the row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three
combinations of divider settings. Any are acceptable for use.
The formula for the effective feedback modulus is: N =[(M +1)
.
6] +A
except when A=0, then: N=(M +1)
.
7
Under all circumstances: A ≤ M
ICS1562B
14
Pin Descriptions - ICS1562B-001
PIN# NAME DESCRIPTION
10 CLK+ Clock out (non-inverted)
9CLK
− Clock out (inverted)
7 LOAD Load output. This output is normally at the CLK frequency divided by N1.
2 XTAL1 Quartz crystal connection 1/external reference frequency input
3 XTAL2 Quartz crystal connection 2
1 AD0 Address/Data Bit 0 (LSB)
16 AD1 Address/Data Bit 1
15 AD2 Address/Data Bit 2
14 AD3 Address/Data Bit 3 (MSB)
8 LD/N2 Divided LOAD output. See text.
4 STROBE Control for address/data latch
13 VDD PLL system power (+5V. See application diagram.)
12 VDDO Output stage power (+5V)
11 IPRG Output stage current set
5,6 VSS Device ground. Both pins must be connected to the same ground potential.
Pin Descriptions - ICS1562B-201
PIN# NAME DESCRIPTION
10 CLK+ Clock out (non-inverted)
9CLK
− Clock out (inverted)
7 LOAD Load output. This output is normally at the CLK frequency divided by N1.
2 XTAL1 Quartz crystal connection 1/external reference frequency input
3 XTAL2 Quartz crystal connection 2
4 DATCLK Data Clock (Input)
16 DATA Serial Register Data (Input)
15 HOLD~
HOLD (Input)
14 BLANK Blanking (Input). See Text.
8 LD/N2 Divided LOAD output/shift clock. See text.
1 EXTFBK External feedback connection for PLL (input). See text.
13 VDD PLL system power (+5V. See application diagram.)
12 VDDO Output stage power (+5V)
11 IPRG Output stage current set
5,6 VSS Device ground. Both pins must be connected.
ICS1562B
15
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ICS1562BM-201-4

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Buy ICS1562BM-201-4
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IC VIDEO CLK SYNTHESIZER 16-SOIC
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